Method and apparatus for calibrating parameters to be used in a digital circuit simulation
AssigneeSun Microsystems, Inc.
InventorsDae Suk Jung, Kyung Lee
Life of this patent
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Abstract
One embodiment of the present invention provides a system for calibrating a model of a digital circuit to account for noise effects between signal lines. The system operates by first fabricating a digital circuit for calibration purposes. Next, an input signal is applied to an aggressor net within the digital circuit. The system then measures how noise from the input signal affects the amplitude of a signal on a victim net within the digital circuit. Finally, the system adjusts parameters of the circuit model using the measured results.
Claims22
A method for calibrating a circuit model to account for noise effects between signal lines, comprising:
- fabricating a digital circuit for calibration purposes;
- applying an input signal to an aggressor net within the digital circuit;
- measuring how noise from the input signal affects an amplitude of a signal on a victim net within the digital circuit;
- and
- adjusting parameters of the circuit model of the digital circuit using results of the measurement.
An apparatus that facilitates calibrating a model for a digital circuit to account for noise effects between signal lines, comprising:
- a digital circuit;
- a victim net within the digital circuit,
- an aggressor net within the digital circuit, wherein the aggressor net is configured to induce a noise signal on the victim net;
- a noise amplifier coupled to the victim net, wherein the noise amplifier is configured to detect the noise signal coupled into the victim net;
- and
- a digitizer configured to digitize an output of the noise amplifier.
An apparatus that facilitates calibrating a model for a digital circuit to account for noise effects between signal lines, comprising:
- a digital circuit;
- a victim net within the digital circuit;
- an aggressor net within the digital circuit, wherein the aggressor net is configured to induce a noise signal on the victim net;
- a noise amplifier coupled to the victim net, wherein the noise amplifier is configured to detect the noise signal coupled into the victim net;
- wherein the noise amplifier further comprises a plurality of level detectors, wherein each level detector is set to detect a specified level of noise;
- a series of inverters following each level detector, wherein the series of inverters amplify and shape an output pulse;
- a digitizer configured to digitize an output of the noise amplifier;
- and
- a latch circuit configured to latch a state of a last inverter of the series of inverters so that the state can be read to determine the output of the level detector.
A means for calibrating a model for a digital circuit to account for noise effects between signal lines:
- a signal application means for applying a signal to an aggressor net within the digital circuit;
- a detecting means for detecting a noise signal coupled into a victim net within the digital circuit;
- a quantizing means for quantizing the noise signal;
- and
- a digitizing means for digitizing the quantized noise signal.
Dependencies are inferred from the claim text.