Random access memory based space time switch architecture

A data switching circuit, comprising:

• at least one input for receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities;
• a plurality of addressable memories, wherein each of the plurality of addressable memories comprises a plurality of memory cells;
• circuitry for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time;
• and
• reading circuitry, coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities alternately to respective multiple output channels;
• wherein M is an integer greater than one;
• wherein each of the data streams consists of an integer number NTS of time slots;
• wherein each of the plurality of addressable memories consists of a number of rows equal to NTS times M;
• wherein the plurality of data streams consists of an integer number Nin of data streams;
• wherein each of the plurality of addressable memories consists of a number of columns equal to a rounded up integer of a quotient equal to Nin divided by M;
• wherein each of the plurality of addressable memories consists of an integer number NC of columns, the columns comprising the memory cells;
• wherein the circuitry for writing writes data to each of the integer number NC of columns at a same time;
• and
• wherein the reading circuitry comprises:
• sense amplifier circuitry;
• and
• switching circuitry coupled between groups of the integer number NC of columns and the sense amplifier circuitry, wherein the switching circuitry is operable to select a subset of columns from each of the groups to which it is coupled and to provide signals from the selected subset to the sense amplifier circuitry.

A data switching circuit, comprising:

• at least one input for receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities;
• a plurality of addressable memories, wherein each of the plurality of addressable memories consists of an integer number NC of columns, the columns comprising memory cells;
• circuitry for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time, wherein the circuitry for writing writes data to each of the integer number NC of columns at a same time;
• and
• reading circuitry, coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities alternately to respective multiple output channels, the reading circuitry comprising:
• sense amplifier circuitry;
• and
• switching circuitry coupled between groups of the integer number NC of columns and the sense amplifier circuitry, wherein the switching circuitry is operable to select a subset of columns from each of the groups to which it is coupled and to provide signals from the selected subset to the sense amplifier circuitry.

A data switching circuit, comprising:

• at least one input for receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities;
• a plurality of addressable memories, wherein each of the plurality of addressable memories comprises a plurality of memory cells;
• circuitry for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time;
• and
• reading circuitry, coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities alternately to respective multiple output channels;
• wherein M is an integer greater than one;
• wherein each of the data streams consists of an integer number NTS of time slots;
• wherein each of the plurality of addressable memories consists of a number of rows equal to NTS times M;
• wherein the plurality of data streams consists of an integer number Nin of data streams;
• and
• wherein each of the plurality of addressable memories consists of a number of columns equal to a rounded up integer of a quotient equal to Nin divided by M.

A data switching circuit, comprising:

• at least one input for receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities and wherein the plurality of data streams are communicated externally toward the data switching circuit at an external frequency;
• a plurality of addressable memories formed on a same integrated circuit, wherein each of the plurality of addressable memories comprises a like-number of rows, each of the rows comprising a plurality of memory cells;
• circuitry for writing into each of the plurality of addressable memories, at a frequency greater than the external frequency, a copy of a same set of data quantities provided by the data streams during a first period of time;
• and
• reading circuitry, coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities alternately to respective multiple output channels.

A data switching circuit, comprising:

• at least one input for receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities;
• a plurality of addressable memories, wherein each of the plurality of addressable memories comprises a plurality of memory cells;
• circuitry for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time;
• and
• reading circuitry, coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities alternately to respective multiple output channels;
• wherein each of the plurality of addressable memories consists of an integer number NC of columns, the columns comprising the memory cells;
• wherein the circuitry for writing writes data to each of the integer number NC of columns at a same time;
• and
• wherein the reading circuitry comprises:
• sense amplifier circuitry;
• and
• switching circuitry coupled between groups of the integer number NC of columns and the sense amplifier circuitry, wherein the switching circuitry is operable to select a subset of columns from each of the groups to which it is coupled and to provide signals from the selected subset to the sense amplifier circuitry.

A method of switching data, comprising:

• receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities;
• writing into each of a plurality of addressable memories, wherein each of the plurality of addressable memories comprises a plurality of single-port memory cells, a copy of a same set of data quantities provided by the data streams during a first period of time;
• and
• reading during a second period of time a number of data quantities from respective ones of the addressable memories and outputting the read data quantities alternately to respective multiple output channels.

A method of switching data, comprising:

• receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities;
• writing into each of a plurality of addressable memories, wherein each of the plurality of addressable memories comprises a plurality of memory cells, a copy of a same set of data quantities provided by the data streams during a first period of time;
• and
• reading during a second period of time a number of data quantities from respective ones of the addressable memories and outputting the read data quantities alternately to respective multiple output channels;
• wherein M is an integer greater than one;
• wherein each of the data streams consists of an integer number NTS of time slots;
• wherein each of the plurality of addressable memories consists of a number of rows equal to NTS times M;
• wherein the plurality of data streams consists of an integer number Nin of data streams;
• wherein each of the plurality of addressable memories consists of a number of columns equal to a rounded up integer of a quotient equal to Nin divided by M;
• wherein each of the plurality of addressable memories consists of an integer number NC of columns, the columns comprising the memory cells;
• wherein the writing step writes data to each of the integer number NC of columns at a same time;
• and
• wherein the reading step comprises selecting a subset of columns from each of a plurality of groups to provide signals from the selected subset to sense amplifier circuitry.

A method of switching data, comprising:

• receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities;
• writing into each of a plurality of addressable memories, wherein each of the plurality of addressable memories consists of an integer number NC of columns and the columns comprise memory cells, a copy of a same set of data quantities provided by the data streams during a first period of time, wherein the writing step writes data to each of the integer number NC of columns at a same time;
• and
• reading during a second period of time a number of data quantities from respective ones of the addressable memories and outputting the read data quantities alternately to respective multiple output channels, the reading step comprising selecting a subset of columns from each of a plurality of groups to provide signals from the selected subset to sense amplifier circuitry.

A method of switching data, comprising:

• receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities;
• writing into each of a plurality of addressable memories, wherein each of the plurality of addressable memories comprises a plurality of memory cells, a copy of a same set of data quantities provided by the data streams during a first period of time;
• and
• reading during a second period of time a number of data quantities from respective ones of the addressable memories and outputting the read data quantities alternately to respective multiple output channels;
• wherein M is an integer greater than one;
• wherein each of the data streams consists of an integer number NTS of time slots;
• wherein each of the plurality of addressable memories consists of a number of rows equal to NTS times M;
• wherein the plurality of data streams consists of an integer number Nin of data streams;
• and
• wherein each of the plurality of addressable memories consists of a number of columns equal to a rounded up integer of a quotient equal to Nin divided by M.

A method of switching data, comprising:

• receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities and wherein the plurality of data streams are communicated externally toward the data switching circuit at an external frequency;
• writing into each of a plurality of addressable memories, wherein the addressable memories are formed on a same integrated circuit and wherein each of the plurality of addressable memories comprises a like-number of rows, each of the rows comprising a plurality of memory cells, at a frequency greater than the external frequency, a copy of a same set of data quantities provided by the data streams during a first period of time;
• and
• reading during a second period of time a number of data quantities from respective ones of the addressable memories and outputting the read data quantities alternately to respective multiple output channels.

A method of switching data, comprising:

• receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities;
• writing into each of a plurality of addressable memories, wherein each of the plurality of addressable memories comprises a plurality of memory cells, a copy of a same set of data quantities provided by the data streams during a first period of time;
• and
• reading during a second period of time a number of data quantities from each respective addressable memory and outputting the read data quantities alternately to respective multiple output channels;
• wherein each of the plurality of addressable memories consists of an integer number NC of columns, the columns comprising the memory cells;
• wherein the circuitry for writing writes data to each of the integer number NC of columns at a same time;
• and
• wherein the reading step comprises selecting a subset of columns from each of a plurality of groups to provide signals from the selected subset to sense amplifier circuitry.