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AssigneeSun Microsystems, Inc.
InventorsMu-Jing Li, Amy Yang
Estimating the term…
Manipulation of a multi-wide object class design layout to facilitate design rule checking or automatic correction of design rule errors is improved by deriving wide class objects from geometries of the design layout, and applying certain rules to non-virtual boundaries of the wide class objects that are not applied to virtual boundaries of the wide class objects. In an exemplary embodiment, the wide class objects are preferably derived by sizing down, then sizing up, each geometry by a sizing factor equal to half the minimum width of the particular wide class object less an amount that preferably corresponds to that represented by a minimum resolution of the design layout. Portions of a geometry that are otherwise excluded as being too narrow in width, but that lie wholly within a correction factor of the boundary of the wide class object otherwise derived, are preferably included to form effective wide class objects.
A method for use in connection with a design layout of an electronic circuit, said design layout comprising a plurality of respective geometries on each of a plurality of layers, said method comprising the steps of:
A method of making a computer readable media product that encodes a design file representation of a design layout of an electronic circuit, said method comprising the steps of:
A method of processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, the design layout comprising a plurality of respective geometries on each of a plurality of layers, said method comprising the steps of:
An electronic circuit fabricated from a design layout representation thereof, said design layout being generated by the steps of:
A computer readable encoding of an electronic circuit design, the computer readable encoding comprising:
An apparatus for processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, said apparatus comprising:
A computer readable encoding of instructions for a computer, said instructions encoding a method for use with a design layout, said method for use in connection with a design layout of an electronic circuit, said design layout comprising a plurality of respective geometries on each of a plurality of layers, said encoded method comprising the steps of:
Dependencies are inferred from the claim text.