Adjustable threshold isolation transistor

A method of forming an integrated circuit comprising:

• growing a pad oxide layer on a substrate;
• growing a silicon nitride layer on the pad oxide;
• etching a first isolation region and a second isolation region from the silicon nitride layer and the pad oxide layer;
• depositing a spacer oxide;
• etching the spacer oxide to form a first opening and a second opening in the first isolation region, and a third opening in the second isolation region;
• implanting a first channel stop implant region in the first opening and a second channel stop implant region in the second opening in the first isolation region, and a third channel stop region in the third opening in the second isolation region;
• removing the remaining spacer oxide;
• growing a field oxide in the first isolation region and the second isolation region;
• removing the silicon nitride layer;
• depositing a polysilicon layer;
• etching the polysilicon layer;
• and
• implanting a plurality of diffusion regions.

A method of forming an integrated circuit comprising:

• providing a first diffusion region, the first diffusion region a source/drain region of a first transistor;
• providing a second diffusion region, the second diffusion region a source/drain region of a second transistor;
• providing a third diffusion region;
• providing an isolation region between the first, second and third diffusion regions;
• and
• selectively implanting a first channel stop implant region, a second channel stop implant region, and a third channel stop implant region in the isolation region, the first channel stop implant region, the second channel stop region, and the third channel stop region separate from each other.