High fMAX deep submicron MOSFET

A method of forming a high fMAX deep submicron MOSFET, comprising the steps of:

• providing a substrate 10 having a MOSFET formed thereon;
• the MOSFET having a source and a drain and including a silicide portion over a gate electrode;
• the gate electrode having a width of from about 500 to 5000 Å;
• forming a first ILD layer over the substrate and the MOSFET;
• chemical-mechanically polishing the first ILD layer to expose the silicide portion over the gate electrode;
• forming a metal gate portion over the planarized first ILD layer and over the silicide portion over the gate electrode 18;
• the metal gate portion having a width of from about 500 to 8000 Å;
• forming a second ILD layer over the metal gate portion and the first ILD layer;
• forming a first metal contact through the second ILD layer contacting the metal gate portion and a second metal contact through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET;
• whereby the width of the metal gate portion reduces Rg and increases the fMAX of the high fMAX deep submicron MOSFET.

A method of forming a high fMAX deep submicron MOSFET, comprising the steps of:

• providing a substrate having a MOSFET formed thereon;
• the MOSFET having a source and a drain and including a silicide portion over a gate electrode;
• the gate electrode having a gate oxide thereunder;
• the gate oxide having a thickness proximate the source and drain to significantly reduce the parasitic capacitance and increase the fmax of the high fMAX deep submicron MOSFET;
• forming a first ILD layer over the substrate and the MOSFET;
• planarizing the first ILD layer to expose the suicide portion over the gate electrode;
• forming a metal gate portion over the planarized first ILD layer and over the silicide portion over the gate electrode;
• the metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode;
• forming a second ILD layer over the metal gate portion and the first ILD layer;
• forming a first metal contact through the second ILD layer contacting the metal gate portion and a second metal contact through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET;
• whereby the width of the metal gate portion reduces Rg and increases the fMAX of the high fMAX deep submicron MOSFET.