# US 2004/0018652 A1 · Modification of circuit features that are interior to a packaged integrated circuit

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- Number: US 2004/0018652 A1
- Document ID: US20040018652A1
- Status: Published application
- Kind: A1
- Application number: 10/206,089
- Filed: 2002-07-25
- Published: 2004-01-29
- Earliest claimed: 2002-07-25
- Assignees: Agilent Technologies, Inc.
- Inventors: Albert An-Bon Yeh; Regina Nora Pabilonia; Robert William Kressin; Wei Liu
- Web page: https://patentgrep.com/patent/US20040018652A1

## CPC

- H10P 74/232: {comprising connection or disconnection of parts of a device in response to a measurement}
- B23K 26/351: for trimming or tuning of electrical components
- H05K 3/0008: {for aligning or positioning of tools relative to the circuit board (H05K3/4638, H05K3/4679 take precedence; for manufacturing assemblages of components H05K13/0015)}
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 70/092: {Adapting interconnections, e.g. making engineering changes, repairing}
- H05K 1/0269: {for visual or optical inspection}
- H05K 1/16: incorporating printed electric components, e.g. printed resistors, capacitors or inductors
- H05K 3/225: {Correcting or repairing of printed circuits (H05K1/0292, H05K3/222, H05K3/288, H05K3/4685 take precedence)}
- H05K 2201/09918: Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
- H05K 2203/107: Using laser light
- H05K 2203/171: Tuning, e.g. by trimming of printed components or high frequency circuits
- H05K 2203/175: Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
- H10W 72/075: {of bond wires}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/551: {Materials of bond wires}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/49117: Conductor or circuit manufacturing
- Y10T 29/49128: Assembling formed circuit to base
- Y10T 29/49131: by utilizing optical sighting device
- Y10T 29/49156: with selective destruction of conductive paths
- Y10T 29/4973: Replacing of defective part
- Y10T 29/49789: Obtaining plural product pieces from unitary workpiece
- Y10T 29/49798: Dividing sequentially from leading end, e.g., by cutting or breaking
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A circuit feature that is interior to a packaged integrated circuit is modified by first identifying a trimming point on the interior circuit feature using an x-ray inspection system. Coordinates of the trimming point are then related to the coordinates of a visible reference marker. The relationship between the visible reference marker and the trimming point is then used to position a cutting tool over the trimming point. Finally, the cutting tool is used to make one or more cuts into the packaged integrated circuit, until the interior circuit feature has been acceptably modified at the trimming point.

## Claims

### Claim 1

A method for modifying a circuit feature that is interior to a packaged integrated circuit, comprising:
a) identifying a trimming point on the interior circuit feature using an x-ray inspection system;
b) relating coordinates of the trimming point to coordinates of a visible reference marker;
c) utilizing the relationship between the visible reference marker and the trimming point to position a cutting tool over the trimming point; and
d) utilizing the cutting tool to make one or more cuts into the packaged integrated circuit, until the interior circuit feature has been acceptably modified at the trimming point.

### Claim 2 (depends on 1)

The method of claim 1, wherein the interior circuit feature is a wirebond.

### Claim 3 (depends on 1)

The method of claim 1, wherein the interior circuit feature is a package trace.

### Claim 4 (depends on 1)

The method of claim 1, wherein the interior circuit feature is a tab.

### Claim 5 (depends on 1)

The method of claim 1, further comprising identifying the visible reference marker using the x-ray inspection system.

### Claim 6 (depends on 1)

The method of claim 1, wherein:
a) the package of the packaged integrated circuit comprises a ball grid array; and
b) the visible reference marker comprises a ball of the ball grid array.

### Claim 7 (depends on 1)

The method of claim 1, wherein the cutting tool is a YAG laser.

### Claim 8 (depends on 1)

The method of claim 1, further comprising, after at least some of the one or more cuts into the packaged integrated circuit, inspecting the interior circuit feature at the trimming point to determine if the interior circuit feature has been acceptably modified.

### Claim 9 (depends on 8)

The method of claim 8, wherein the inspections of the interior circuit feature are performed using the x-ray inspection system.

### Claim 10 (depends on 8)

The method of claim 8, wherein, after at least some inspections of the interior circuit feature at the trimming point, one or more characteristics of the cutting tool are adjusted.

### Claim 11 (depends on 1)

The method of claim 1, further comprising, after the interior circuit feature is acceptably modified at the trimming point, utilizing epoxy compound to seal a hole formed during cutting.

### Claim 12 (depends on 1)

The method of claim 1, further comprising, after the interior circuit feature is acceptably modified at the trimming point, filling with a conductive material, at least a lower portion of a hole formed during cutting.

### Claim 13 (depends on 1)

The method of claim 1, wherein acceptably modifying the interior circuit feature comprises severing the interior circuit feature.

### Claim 14 (depends on 1)

The method of claim 1, wherein the visible reference marker is located on the package of the packaged integrated circuit.

### Claim 15 (depends on 1)

The method of claim 1, wherein the visible reference marker is located on a printed circuit board on which the packaged integrated circuit is mounted.

### Claim 16

A parallel design process for integrated circuits, comprising:
a) while designing an integrated circuit, laying out plural circuit features to be evaluated;
b) fabricating and packaging a plurality of the integrated circuits;
c) for a first of the packaged integrated circuits,
i) identifying a circuit feature that is interior to the packaged integrated circuit, wherein the interior circuit feature is coupled to at least one of the plural circuit features to be evaluated;
ii) identifying a trimming point on the interior circuit feature using an x-ray inspection system;
iii) relating coordinates of the trimming point to coordinates of a visible reference marker;
iv) utilizing the relationship between the visible reference marker and the trimming point to position a cutting tool over the trimming point; and
v) utilizing the cutting tool to make one or more cuts into the first of the packaged integrated circuits, until the interior circuit feature has been acceptably modified at the trimming point; and
d) comparing operation of the first of the packaged integrated circuits to operation of a second of the packaged integrated circuits.

### Claim 17 (depends on 16)

The process of claim 16, further comprising identifying the visible reference marker using the x-ray inspection system.

### Claim 18 (depends on 16)

The process of claim 16, wherein the second of the packaged integrated circuits has been modified differently than the first of the packaged integrated circuits.

### Claim 19

A parallel design process for integrated circuits, comprising:
a) while designing a package for an integrated circuit, laying out plural package circuit features to be evaluated;
b) fabricating and packaging a plurality of the integrated circuits;
c) for a first of the packaged integrated circuits,
i) identifying one of the plural package circuit features to be modified;
ii) identifying a trimming point on the identified package circuit feature, using an x-ray inspection system;
iii) relating coordinates of the trimming point to coordinates of a visible reference marker;
iv) utilizing the relationship between the visible reference marker and the trimming point to position a cutting tool over the trimming point; and
v) utilizing the cutting tool to make one or more cuts into the first of the packaged integrated circuits, until the identified package circuit feature has been acceptably modified at the trimming point; and
d) comparing operation of the first of the packaged integrated circuits to operation of a second of the packaged integrated circuits.

### Claim 20 (depends on 19)

The process of claim 19, further comprising identifying the visible reference marker using the x-ray inspection system.

### Claim 21 (depends on 19)

The process of claim 19, wherein the second of the packaged integrated circuits has been modified differently than the first of the packaged integrated circuits.

### Claim 22

A method for tuning a packaged integrated circuit, comprising:
a) incorporating into a packaged integrated circuit design, at least one tunable circuit feature;
b) fabricating a packaged integrated circuit in accordance with said packaged integrated circuit design;
c) identifying a trimming point on the tunable circuit feature of said packaged integrated circuit, using an x-ray inspection system;
d) relating coordinates of the trimming point to coordinates of a visible reference marker;
e) utilizing the relationship between the visible reference marker and the trimming point to position a cutting tool over the trimming point; and
f) utilizing the cutting tool to make one or more cuts into the packaged integrated circuit, until the tunable circuit feature has been acceptably modified at the trimming point.

### Claim 23 (depends on 22)

The method of claim 22, wherein the tunable circuit feature is a package trace that is coupled to an optional circuit feature.

### Claim 24 (depends on 22)

The method of claim 22, wherein the tunable circuit feature is a resistor network.

### Claim 25 (depends on 22)

The method of claim 22, wherein the tunable circuit feature is a wirebond that is coupled to an optional circuit feature.

### Claim 26 (depends on 22)

The method of claim 22, wherein acceptable modification of the tunable circuit feature comprises removal of the tunable circuit feature.

### Claim 27 (depends on 22)

The method of claim 22, further comprising identifying the visible reference marker using the x-ray inspection system.

### Claim 28

A method for producing batches of packaged integrated circuits with differing characteristics, comprising:
a) designing an integrated circuit and package therefor that incorporate at least one optional circuit feature;
b) fabricating a plurality of packaged integrated circuits as designed;
c) dividing the plurality of packaged integrated circuits into at least two batches, and for the packaged integrated circuits of a first batch,
i) identifying a circuit feature that enables one of the optional circuit features, wherein the circuit feature is interior to the packaged integrated circuits of the first batch;
ii) identifying a trimming point on the interior circuit feature using an x-ray inspection system;
iii) relating coordinates of the trimming point to coordinates of a visible reference marker;
iv) utilizing the relationship between the visible reference marker and the trimming point to position a cutting tool over the trimming point; and
v) utilizing the cutting tool to make one or more cuts into the packaged integrated circuits of the first batch, until the interior circuit feature has been acceptably modified in at least some of the packaged integrated circuits of the first batch, thereby creating a batch of packaged integrated circuits that differs from other batches of packaged integrated circuits.

### Claim 29 (depends on 28)

The method of claim 28, wherein steps i)-iii) are performed for only some of the packaged integrated circuits of the first batch.