Analog delay locked loop characterization technique
OwnerKian Chong, Dean Liu +1inventors
InventorsKian Chong, Dean Liu, Claude Gauthier
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Abstract
A delay locked loop characterization technique for automatically characterizing a delay locked loop is provided. The technique tests the delay locked loop using a top-down approach in order to ensure the robustness of the delay locked loop. Top-level testing involves testing the performance of the delay locked loop in different process corners, and the results obtained from the top-level testing are then used to test sub-components of the delay locked loop.
Claims13
A method for characterizing a delay locked loop, comprising:
- top-level testing the delay locked loop to generate a waveform representative of an operation of the delay locked loop;
- and
- bottom-level testing a circuit in the delay locked loop dependent on the waveform.
A computer-readable medium having recorded therein instructions executable by processing, the instructions for:
- top-level testing a delay locked loop to generate a waveform representative of an operation of the delay locked loop;
- and
- bottom-level testing a circuit in the delay locked loop dependent on the waveform.
A computer system, comprising:
- a processor;
- a memory;
- and
- instructions, residing in the memory and executable by the processor, for top-level testing a delay locked loop to generate a waveform representative of an operation of the delay locked loop, and bottom-level testing a circuit in the delay locked loop dependent on the waveform.
A method for characterizing a delay locked loop, comprising:
- step for top-level testing the delay locked loop to generate a waveform representative of an operation of the delay locked loop;
- and
- step for bottom-level testing a circuit in the delay locked loop dependent on the waveform.
Dependencies are inferred from the claim text.