Phase and frequency lock detector

A lock detector coupled to a phase-locked loop (PLL), the PLL being configured for receiving a reference signal and locking a feedback signal to the reference signal, the lock detector being configured for detecting lock between the reference and feedback signals, the lock detector comprising:

• a pulse generator configured for generating a pulse train from the reference signal, each pulse of the pulse train corresponding to at least one of rising and falling edges of the reference signal in each period of the reference signal;
• a mask generator coupled to the PLL for receiving at least a PLL output signal and generating a mask signal from the PLL output signal such that the mask signal has a mask state around at least one of rising and falling edges of the feedback signal in each period of the feedback signal, wherein the PLL output signal is substantially in phase with the feedback signal;
• and
• a logical gate coupled to the pulse generator and the mask generator, the logical gate receiving the pulse train from the pulse generator and receiving the mask signal from the mask generator, the logical gate generating an incrementing pulse signal having one or more incrementing pulses by combining the pulse train with the mask signal.

A method for detecting lock between first and second signals, the method comprising the steps of:

• generating a pulse train from the first signal, each pulse of the pulse train corresponding to at least one of rising and falling edges of the first signal in each period of the first signal;
• generating a mask signal from the second signal such that the mask signal has a mask state around at least one of rising and falling edges of the second signal in each period of the second signal;
• generating an incrementing pulse signal having one or more incrementing pulses by combining the pulse train with the mask signal;
• and
• detecting lock between the first and second signals from the incrementing pulse signal.

A method for detecting lock between a reference signal inputted to a phase-locked loop (PLL) and a feedback signal in the PLL, the method comprising the steps of:

• generating a pulse train from the reference signal, each pulse of the pulse train corresponding to at least one of rising and falling edges of the reference signal in each period of the reference signal;
• generating a mask signal from the PLL output signal such that the mask signal has a mask state around at least one of rising and falling edges of the feedback signal in each period of the feedback signal, wherein the PLL output signal is substantially in phase with the feedback signal;
• generating an incrementing pulse signal having one or more incrementing pulses by combining the pulse train with the mask signal;
• and
• detecting lock between the reference and feedback signals from the incrementing pulse signal.

A computer program product for detecting lock between first and second signals, the computer program product having a medium with a computer program embodied thereon, the computer program comprising:

• computer program code for generating a pulse train from the first signal, each pulse of the pulse train corresponding to at least one of rising and falling edges of the first signal in each period of the first signal;
• computer program code for generating a mask signal from the second signal such that the mask signal has a mask state around at least one of rising and falling edges of the second signal in each period of the second signal;
• computer program code for generating an incrementing pulse signal having one or more incrementing pulses by combining the pulse train with the mask signal;
• and
• computer program code for detecting lock between the first and second signals from the incrementing pulse signal.

A computer program product for detecting lock between a reference signal inputted to a phase-locked loop (PLL) and a feedback signal in the PLL, the computer program product having a medium with a computer program embodied thereon, the computer program comprising:

• computer program code for generating a pulse train from the reference signal, each pulse of the pulse train corresponding to at least one of rising and falling edges of the reference signal in each period of the reference signal;
• computer program code for generating a mask signal from the PLL output signal such that the mask signal has a mask state around at least one of rising and falling edges of the feedback signal in each period of the feedback signal, wherein the PLL output signal is substantially in phase with the feedback signal;
• computer program code for generating an incrementing pulse signal having one or more incrementing pulses by combining the pulse train with the mask signal;
• and
• computer program code for detecting lock between the reference and feedback signals from the incrementing pulse signal.