US 2004/0017698 A1Published application

Refined gate coupled noise compensation for open-drain output from semiconductor device

AssigneeMicron Technology, Inc.

InventorBrian W. Huber

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Abstract

An open-drain output circuit for a semiconductor device is provided with compensation circuitry for minimizing fluctuations in a regulated gate voltage applied to the gate of an open-drain output transistor. In one embodiment, a compensation voltage is derived from an input signal to the output circuit and applied to one terminal of a capacitor. A second terminal of the capacitor is coupled to the gate of the open-drain output transistor. The compensation circuit comprises at least one pull-up transistor and at least one pull-down transistor coupled to a first terminal of the capacitance. The capacitance couples the compensation voltage to the gate of the output transistor, thereby compensating for capacitive coupling noise induced in constant-voltage gate signal applied to the gate of the output transistor upon assertion of the input signal to the output circuit.

Claims43

Dependent claims

An open-drain output circuit for a semiconductor device, comprising:

an output transistor having a first terminal coupled to an output pad of said semiconductor device, a second terminal selectively coupled to ground potential via a source-to-drain path of a second transistor, and having a gate terminal coupled to a voltage regulator output node and receiving a substantially constant voltage signal therefrom;
an input terminal for receiving an input signal, said input terminal coupled to a gate terminal of said second transistor, and coupled to a gate terminal of a pull-up transistor, said pull-up transistor being coupled between a compensation node and a voltage supply and being responsive to said input signal to selectively pull up the voltage on said compensation node;
at least one inverter receiving said input signal and generating a first complementary input signal;
a first pull-down transistor coupled between said compensation node and ground potential, said first pull-down transistor being responsive to said first complementary input signal applied to its gate terminal to selectively pull down the voltage on said compensation node;
and
a capacitance disposed between said compensation node and said voltage regulator output node;
wherein said capacitance couples said voltage on said compensation node to said voltage regulator output node to compensate for fluctuations in said substantially constant voltage signal occurring upon assertion of said input signal.

4 more elements

A method of driving an output signal at an open-drain output of a semiconductor device, comprising:

providing an output transistor having a first terminal coupled to an output pad of said semiconductor device, a second terminal selectively coupled to ground potential via a source-to-drain path of a second transistor, and having a gate terminal coupled to a voltage regulator output node and receiving a substantially constant voltage signal therefrom;
receiving an input signal at an input terminal, said input terminal being coupled to a gate terminal of said second transistor, and coupled to a gate terminal of a pull-up transistor;
disposing said pull-up transistor between a compensation node and a voltage supply and being responsive to said input signal to selectively pull up the voltage on said compensation node;
receiving said input signal at at least one inverter and generating a first complementary input signal;
disposing a first pull-down transistor between said compensation node and ground potential, said first pull-down transistor being responsive to said first complementary input signal applied to its gate terminal to selectively pull down the voltage on said compensation node;
and
coupling a capacitance between said compensation node and said voltage regulator output node;
wherein said capacitance couples said voltage on said compensation node to said voltage regulator output node to compensate for fluctuations in said substantially constant voltage signal occurring upon assertion of said input signal.

5 more elements

A semiconductor memory device having at least one open-drain output, comprising:

an array of rows and columns of memory cells each adapted to store a bit of data;
address decoding circuitry for selecting a memory cell from which a bit of data is read;
an output transistor having a first terminal coupled to an output pad of said semiconductor device, a second terminal selectively coupled to ground potential via a source-to-drain path of a second transistor, and having a gate terminal coupled to a voltage regulator output node and receiving a substantially constant voltage signal therefrom;
an input terminal for receiving an input signal corresponding to said bit of data from said selected memory cell, said input terminal coupled to a gate terminal of said second transistor, and coupled to a gate terminal of a pull-up transistor, said pull-up transistor being coupled between a compensation node and a voltage supply and being responsive to said input signal to selectively pull up the voltage on said compensation node;
at least one inverter receiving said input signal and generating a first complementary input signal;
a first pull-down transistor coupled between said compensation node and ground potential, said first pull-down transistor being responsive to said first complementary input signal applied to its gate terminal to selectively pull down the voltage on said compensation node;
and
a capacitance disposed between said compensation node and said voltage regulator output node;
wherein said capacitance couples said voltage on said compensation node to said voltage regulator output node to compensate for fluctuations in said substantially constant voltage signal occurring upon assertion of said input signal.

6 more elements

An open-drain output circuit for a semiconductor device, comprising:

an output transistor having a first terminal coupled to an output pad of said semiconductor device, a second terminal selectively coupled to ground potential via a source-to-drain path of a second transistor, and having a gate terminal coupled to a voltage regulator output node and receiving a substantially constant voltage signal therefrom;
an input terminal for receiving an input signal, said input terminal coupled to a gate terminal of said second transistor, and coupled to a gate terminal of a plurality of pull-up transistors, a first of said plurality of pull-up transistors being coupled between a compensation node and a voltage supply and being responsive to said input signal to selectively pull up the voltage on said compensation node, and at least a second one of said plurality of pull-up transistors being selectively coupled between said compensation node and a voltage supply;
at least one inverter receiving said input signal and generating a first complementary input signal;
a first pull-down transistor coupled between said compensation node and ground potential, said first pull-down transistor being responsive to said first complementary input signal applied to its gate terminal to selectively pull down the voltage on said compensation node;
at least a second pull-down transistor selectively coupled between said compensation node and ground potential;
a capacitance disposed between said compensation node and said voltage regulator output node;
a first correction circuit coupled to said voltage supply and said at least a second one of said plurality of pull-up transistors, said first correction circuit being responsive to at least one code bit to selectively couple said at least a second one of said plurality of pull-up transistors to said voltage supply, such that said at least a second one of said plurality of pull-up transistors is responsive to said input signal to selectively pull up the voltage on said compensation node;
and
a second correction circuit coupled to ground potential and to said at least a second pull-down transistor, said second correction circuit being responsive to said at least one code bit to selectively couple said at least a second one of said plurality of pull-down transistors to said voltage supply, such that said at least a second one of said plurality of pull-down transistors is responsive to said input signal to selectively pull down the voltage on said compensation node;
wherein said capacitance couples said voltage on said compensation node to said voltage regulator output node to compensate for fluctuations in said substantially constant voltage signal occurring upon assertion of said input signal.

7 more elements

Dependencies are inferred from the claim text.