Circuit arrangement with semiconductor elements arranged in chips
AssigneeSiemens Aktiengesellschaft
InventorsGerd Auerswald, Gunter Ludwig
Life of this patent
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Abstract
A circuit arrangement with semiconductor elements arranged in chips is described. The circuit arrangement is characterized by at least one metal body (s1) for electrically contacting the semiconductor elements and for dissipating the heat produced by the semiconductor elements, said metal body (s1) being adapted to simultaneously function as the support for the semiconductor elements and the chips (c1) of the semiconductor elements being fastened on the body (s1).
Claims17
Circuit arrangement with semiconductor elements arranged in chips comprising:
- at least one metallic body for electrical contacting of the semiconductor elements and for dissipation of the heat generated in the semiconductor elements, whereby the metallic body or bodies are designed in such a way that the metallic body or bodies simultaneously serve as carriers for the semiconductor elements, and the chips are fastened to the metallic body or bodies, and wherein
- the semiconductor elements comprise first semiconductor elements which are switched in parallel,
- the body or bodies include a first body to which the chips of the first semiconductor element are fastened,
- at least a first metallic bus body is provided as a terminal for a control module,
- the control connections of the first semiconductor elements are electrically connected to the first bus body with the aid of bond wires,
- the semiconductor elements include second semiconductor elements switched in parallel,
- the body or bodies include a second body to which the chips of the second semiconductor element are fastened and which is arranged next to the first body,
- a second metallic bus body is provided as a terminal for the control module, and
- the control terminals of the second semiconductor elements are connected to the second bus body with the aid of bond wires.
Circuit arrangement comprising:
- a plurality of semiconductor elements,
- at least one metallic body for electrical contacting of the semiconductor elements and for dissipation of the heat generated in the semiconductor elements, whereby the metallic body or bodies are designed in such a way that the metallic body or bodies simultaneously serve as carriers for the semiconductor elements, and the semiconductor elements are fastened to the metallic body or bodies,
- first semiconductor elements of the semiconductor elements which are switched in parallel,
- a first body of the at least one metallic body to which the first semiconductor elements are fastened,
- at least a first metallic bus body as a terminal for a control module,
- control connections of the first semiconductor elements which are electrically connected to the first bus body by means of bond wires,
- second semiconductor elements of the semiconductor elements which are switched in parallel,
- a second body of the at least one metallic body to which the second semiconductor elements are fastened and which is arranged next to the first body,
- a second metallic bus body as a terminal for the control module, and
- control terminals of the second semiconductor elements which are connected to the second bus body by means of bond wires.
Method of manufacturing a circuit arrangement comprising the steps of:
- providing a plurality of semiconductor elements,
- providing a cooling body;
- arranging at least a first metallic body on said cooling body to which first semiconductor elements of said semiconductor elements are fastened,
- arranging at least a first metallic bus body on said cooling body as a terminal for a control module,
- coupling control connections of the first semiconductor elements to the first bus body by means of bond wires,
- arranging at least a second metallic body next to the first body to which second semiconductor elements of said semiconductor elements are fastened,
- arranging a second metallic bus body as a terminal for the control module, and
- connecting control terminals of the second semiconductor elements to the second bus body by means of bond wires.
Dependencies are inferred from the claim text.