Accelerating scan test by re-using response data as stimulus data

A method of using first and second scan cells respectively coupled to first and second electrically separate nodes of a target circuit, comprising:

• transferring a signal from the second scan cell to an input of the first scan cell other than a scan input of the first scan cell;
• and
• receiving the signal at the first scan cell.

A method of testing a target circuit, comprising:

• transferring a sequence of test patterns between the target circuit and a memory;
• and
• transferring the sequence of test patterns to a signature analyzer that is separate from the memory.

A method of using a scan cell to evaluate a target circuit, comprising:

• receiving at an input of the scan cell an output signal from the target circuit;
• and
• compressing the output signal with a signal from a scan output of the scan cell.

A method of using a scan path to test target circuitry, comprising:

• using the scan path to test completely a first portion of the target circuitry according to a predetermined test methodology, including scanning from a test controller into the scan path a minimum number of bits necessary to test completely the first portion of the target circuitry according to the predetermined test methodology;
• and
• using the scan path to test a second portion of the target circuitry according to the predetermined test methodology, including completing the testing of the second portion of the target circuitry at least as early as completion of the testing of the first portion of the target circuitry.

A method of generating test stimulus patterns for use in scan testing target circuitry, comprising:

• while the target circuitry is being scan tested, using the target circuitry to generate test stimulus patterns for use in its own scan test;
• and
• scanning through a scan path the test stimulus patterns generated by the target circuitry.

A method of operating a scan path having therein both a capture-shift scan cell and a capture-shift-update scan cell, comprising:

• rendering an update memory of the capture-shift-update scan cell transparent;
• and
• thereafter, outputting desired stimulus data simultaneously from both of the scan cells to a target circuit in response to a common control signal.

A method of operating a scan path, the scan path including a plurality of series-connected scan cells respectively coupled to a plurality of nodes of a target circuit to be evaluated, a first of the scan cells having a scan input arranged to receive data generated externally of the scan path, comprising:

• operating a switch to isolate the scan input of the first scan cell from the externally generated data and to connect the scan input of the first scan cell directly to a second of the scan cells;
• and
• scanning data from the second scan cell into the first scan cell via the switch.

A method of designing a logic circuit for testability, comprising:

• identifying a logic signal which, when input to the logic circuit as presently designed, causes the logic circuit to produce an undefined logic output;
• and
• thereafter, altering the logic circuit such that the identified logic signal, when input to the altered logic circuit, causes the altered logic circuit to produce a predetermined logic output that can be used as a test input for testing another logic circuit.

A method of operating a scan path, comprising:

• scanning a first test stimulus into a predetermined position in the scan path in response to a first number of scan clock cycles;
• and
• scanning a second test stimulus into the predetermined position in the scan path in response to a second number of scan clock cycles that differs from the first number of scan clock cycles.

A method of using a scan path to test target circuitry, comprising:

• scanning into the scan path from a source external to the scan path a first test stimulus;
• and
• thereafter, applying the first test stimulus from the scan path to a first portion of the target circuitry while simultaneously applying from the scan path to a second portion of the target circuitry a second test stimulus which is independent of the external source.