System verifying apparatus and method

Abstract

An apparatus which verifies a system comprising at least a microprocessor includes a first simulator which verifies a test program for the system. The apparatus further includes a second simulator which verifies a functional description of the system to extract first event information that expresses a verification item relating to an operational specification of the system, as an event. The apparatus further includes a comparator which compares results of verification carried out by the second simulator with results of verification carried out by the first simulator, and a checker which checks whether or not the verification item is met on the basis of a second event information resulting from the verification carried out by the second simulator and the first event information if the results of the verification carried out by the first simulator match the results of the verification carried out by the second simulator.

Dependencies are inferred from the claim text.