Hierarchical test methodology for multi-core chips

Abstract

A multi-core chip (MCC) having a plurality of processor cores includes a hierarchical testing architecture compliant with the IEEE 1149.1 Joint Test Action Group (JTAG) standard that leverages existing standard testing architectures within each processor core to allow for chip level access to schedule built-in self test (BIST) operations for the cores. The MCC includes boundary scan logic, a chip-level JTAG-compliant test access port (TAP) controller, a chip-level master BIST controller, and a test pin interface. Each processor core includes a JTAG-compliant TAP controller and one or more BIST enabled memory arrays. The chip TAP controller includes one or more user defined registers, including a core select register and a test mode register. The core select register stores a plurality of core select bits that select corresponding processor cores for BIST operations.

Dependencies are inferred from the claim text.