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US 2004/0006725 A1Published application
Method and apparatus for improving network router line rate performance by an improved system for error checking
AssigneeIntel Corporation
InventorsSridhar Lakshmanamurthy, Charles E. Narad, Lawrence B. Huston, Yim Pun, Kin-Yip Liu
Life of this patent
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Abstract
A method and apparatus for improving network router line rate performance by an improved system for error correction is described. In an embodiment of the present invention, error correction is performed by a hardware-based system within the processing engine of a router's network processor.
Claims30
A system for network data transfer comprising:
- an intermediate device to pass a data set from a first device to at least one of a plurality of locations in a memory device, said intermediate device having an execution unit and an error correction device, wherein
- said execution unit is to determine where in said memory device to pass said data set;
- and
- said error correction device is a hardware device to operate in parallel with said execution unit.
1 more element
A method for network data transfer comprising:
- transferring a data set, by an intermediate device, from a first device to at least one of a plurality of locations in a memory device, said intermediate device having an execution unit and an error correction device;
- determining, by said execution unit, where in said memory device to transfer said data set;
- and
- processing said data set, by said error correction device, in parallel with said execution unit.
1 more element
An apparatus for network data transfer comprising:
- a processing engine to forward a data set, having an error check term, from a media interface to at least one location in a memory device, said media interface to translate said data set from a first protocol to a second protocol and said processing engine including an execution unit to determine where in said memory device to forward said data set;
- and
- an error-correction device including a linear shift register to compare said error check term to a value computed by said linear shift register.
A system for network data transfer comprising:
- a line card including a processing engine, said processing engine to forward a data set having an error check term from a media interface to at least one location in a memory device;
- and
- an error-correction device including a linear shift register to compare said error check term to a value computed by said linear shift register, wherein
- said media interface is to translate said data set from a first protocol to a second protocol and is coupled to a network;
- and
- said processing engine includes an execution unit to determine where in said memory device to forward said data set.
3 more elements
Dependencies are inferred from the claim text.