Network processor performance monitoring system and method
AssigneeIntel Corporation
InventorsSridhar Lakshmanamurthy, Mark B. Rosenbluth, Jeen-Yuan Miin
Life of this patent
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Abstract
Embodiments described herein provide a system and method that advantageously reduces the number of internal signals required to monitor the performance of a network processor. A plurality of events may be selected from a predetermined number of design unit events, and a plurality of signals may be selected from a predetermined number of design unit signals. A plurality of counters may be associated with the plurality of signals, and for each of the plurality of signals, a number of event occurrences may be counted and sent to a processor unit.
Claims26
A network processor performance monitoring system, comprising:
- a core processor;
- a plurality of design units, each having a plurality of event multiplexers, coupled to the core processor;
- and
- a performance monitoring unit, coupled to the core processor, including:
- a plurality of counter blocks each having a counter,
- a plurality of event bus multiplexers coupled to the plurality of counter blocks and the plurality of design unit event multiplexers, and
- a control block coupled to the plurality of event bus multiplexers and the plurality of design units.
A method for monitoring network processor performance, comprising:
- selecting a plurality of events from a predetermined number of design unit events;
- selecting a plurality of signals from a predetermined number of design unit signals;
- associating a plurality of counters with the plurality of signals;
- and
- for each of the plurality of signals:
- counting a number of event occurrences, and
- sending the number of event occurrences to a processor unit.
A network processor performance monitoring apparatus, comprising:
- a processor bus interface;
- a control bus interface;
- a plurality of event bus interfaces;
- a plurality of counter blocks, each having a counter, coupled to the processor bus interface;
- a plurality of event bus multiplexers coupled to the plurality of counter blocks and the plurality of event bus interfaces;
- and
- a control block coupled to the processor bus interface, the control bus interface and the plurality of event bus multiplexers.
A computer-readable medium storing instructions adapted to be executed by a processor, the instructions comprising:
- selecting a plurality of events from a predetermined number of design unit events;
- selecting a plurality of signals from a predetermined number of design unit signals;
- associating a plurality of counters with the plurality of signals;
- and
- for each of the plurality of signals:
- counting a number of event occurrences, and
- sending the number of event occurrences to a processor unit.
Dependencies are inferred from the claim text.