Method and apparatus for recovery from loss of lock step
AssigneeHewlett-Packard Development Company, L.P.
InventorKevin David Safford
Life of this patent
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Abstract
An apparatus, operating on an advanced multi-core processor architecture, and a corresponding method, are used to enhance recovery from loss of lock step in a multi-processor computer system. The apparatus for recovery from loss of lock step includes multiple processor units operating in the computer system, each of the processor units having at least two processor units operating in lock step, and at least one idle processor unit operating in lock step; and a controller coupled to the two processor units operating in lock step and the idle processor unit. The controller includes mechanisms for copying an architected state of each of the two lock step processor units to the idle processor unit.
Claims20
An apparatus for recovery from loss of lock step in a computer system, comprising:
- a plurality of processor units operating in the computer system, comprising:
- at least one logical processor unit operating in lock step, and
- at least one idle logical processor unit operating in lock step;
- and
- a controller coupled to at least the at least one logical processor unit operating in lock step and the at least one idle logical processor unit, the controller comprising means for copying an architected state of each of the at least one logical processor unit to the at least one idle logical processor unit.
A method for recovery from loss of lock step in a computer system, comprising:
- receiving a loss of lock step signal from a processor unit;
- receiving a notice from the loss of lock step processor unit to take the loss of lock step processor unit off line;
- and
- moving an architected state of the loss of lock step processor unit to a spare processor unit, wherein the spare processor unit becomes an active processor unit in the computer system.
An apparatus to recover from a loss of lock step in a multiprocessor computer system, wherein two or more processor units operate in lock step, comprising:
- in each of the two or more processor units operating in lock step:
- means for detecting a loss of lock step initiating event, and
- means for signaling an impending loss of lock step;
- and
- means for moving an architected state of a processor unit having the loss of lock step initiating event to a spare processor unit, the spare processor unit operating idle in lock step.
A method for recovering from a loss of lock step operation in a multi-processor computer system, comprising:
- detecting a loss of lock step initiating event in a processor;
- signaling an impending loss of lock step;
- copying an architected state of the loss of lock step processor to a spare processor;
- and
- idling the loss of lock step processor.
Dependencies are inferred from the claim text.