Mirrored tag snoop optimization
AssigneeDell Products L.P.
InventorsRichard W. Schuckle, Gary Verdun
Life of this patent
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Abstract
A method and system for reducing snoop traffic on a processor bus coupling a cache memory and a processor. The processor is unable to perform a snoop operation while operating in a lower power state to conserve power. A copy of cache tag is maintained in a memory controller coupled to the processor bus. The memory controller performs snoop operations on the copy of the cache tag while the processor is placed in the lower power state. The processor exits the lower power state when an access to a modified cached line occurs.
Claims28
A method of reducing power consumed by a processor in an information handling system having the processor coupled to a memory controller, the method comprising the step of:
- providing a processor having a lower power state and in a higher power state, wherein the processor does not perform a snoop operation while in the lower power state;
- and
- performing the snoop operation with a memory controller, wherein the memory controller performs the snoop operation when the processor is in the lower power state.
A method of reducing snoop traffic on a processor bus coupling a cache memory and a processor, the method comprising the steps of:
- maintaining a copy of a cache tag in a memory controller, wherein the memory controller is coupled to a processor bus;
- performing a snoop operation with the memory controller on the copy of the cache tag while the processor is in a lower power state, wherein the processor does not perform the snoop operation while operating in the lower power state;
- and
- changing the processor from the lower power state to the higher power state when an access to a modified cached line occurs.
An information handling system, comprising:
- a processor, wherein the processor performs a snoop operation when in a higher power state and does not perform the snoop operation when in a lower power state;
- a memory coupled to the processor;
- a cache memory coupled to the processor and the memory;
- a processor bus, wherein the processor bus is coupled to the processor and a memory controller;
- and
- the memory controller being enabled to perform the snoop operation while the processor is in the lower power state.
A information handling system comprising:
- a processor;
- a memory coupled to the processor;
- a cache memory coupled to a processor bus, wherein the processor bus is coupled to the processor and a memory controller;
- and
- wherein the memory controller is adapted to:
- store a copy of a cache tag in the memory controller;
- perform a snoop operation with the memory controller on the copy of the cache tag when the processor is in a lower power state and thereby does not perform the snoop operation;
- and
- changing the processor from the lower power state to the higher power state when an access to a modified cached line occurs.
A computer-readable medium having a computer program accessible therefrom, wherein the computer program comprises instructions for:
- maintaining a processor of a information handling system in a lower power state, wherein the processor does not perform a snoop operation while in the lower power state;
- and
- redirecting the snoop operation from the processor to a memory controller of the information handling system, wherein the redirected snoop operation enables a reduction in power consumed by the processor maintained in the lower power state.
A computer-readable medium having a computer program accessible therefrom, wherein the computer program comprises instructions for:
- storing a copy of a cache tag in a memory controller of a information handling system, wherein the memory controller is coupled to a processor included in the information handling system;
- performing a snoop operation with the memory controller on the copy of the cache tag while the processor is placed in a lower power state, wherein the processor does not perform the snoop operation while in the lower power state;
- and
- changing the processor from the lower power state to the higher power state when an access to a modified cached line occurs.
Dependencies are inferred from the claim text.