Processor and instruction control method
AssigneeFujitsu Limited
InventorToshio Yoshida
Life of this patent
Estimating the term…
Abstract
A latest register update buffer which stores latest register update data is allocated and prepared every general register for storing source data. A latest register update processing unit stores a value in the general register as latest register update data into the latest register update buffer when a register update instruction is not speculatively executed, and overwrites a result of the speculative execution when the instruction is speculatively executed. Upon instruction decoding, a matching processing unit reads out the latest register update data from the latest register update allocation buffer and stores it into a data area in a reservation station.
Claims24
A processor comprising:
- a buffer which is allocated every general register for storing source data and stores latest register update data;
- a buffer control unit which stores said latest register update data into said buffer in accordance with the presence or absence of speculative execution of a register update instruction;
- and
- a storage control unit which reads out the latest register update data from said buffer and stores it into a data area in a reservation station upon instruction decoding.
An instruction control method of a processor which executes instructions by dynamic pipeline scheduling, comprising:
- a buffer control step wherein latest register update data is stored into a buffer which is allocated every general register for storing source data in accordance with the presence or absence of speculative execution of a register update instruction;
- and
- a storage control step wherein said latest register update data is read out from said buffer and stored into a data area in a reservation station upon instruction decoding.
A processor comprising:
- a buffer which is allocated every register for storing a condition code and stores latest condition code register update data;
- a buffer control unit which sets the latest condition code register update data into said buffer in accordance with the presence or absence of speculative execution of a condition code register update instruction;
- and
- a storage control unit which reads out the latest condition code register update data from said buffer and stores it into a condition code data area in a reservation station upon instruction decoding.
An instruction control method of a processor which executes instructions by dynamic pipeline scheduling, comprising:
- a buffer control step wherein latest condition code register update data is set into a buffer which is allocated every register for storing a condition code in accordance with the presence or absence of speculative execution of a condition code register update instruction;
- and
- a storage control step wherein the latest condition code register update data is read out from said buffer and stored into a condition code data area in a reservation station upon instruction decoding.
Dependencies are inferred from the claim text.