Register renaming for dynamic multi-threading
AssigneeIntel Corporation
InventorsEdward A. Brekelbaum, Jeffrey P. Rupley II
Life of this patent
Estimating the term…
Abstract
A register renaming technique for dynamic multithreading. One disclosed embodiment includes a register map to store up to M×N values to map M registers for N threads. A set of N values, one per thread, and a set of state bits is associated with each of the M registers. Each set of state bits indicates which of the N values per register are valid and whether ones of the N sets of values have been written by a dynamic execution thread. In response to termination of a dynamic execution thread, recovery logic may update state bits associated with ones of the M registers that were written to during dynamic execution.
Claims30
An apparatus comprising:
- a register map to store up to M×N values to map M registers for N threads, a set of N values being associated with each of the M registers;
- a plurality of M sets of state bits, each set of state bits being associated with one of said M registers and to indicate which of N values are valid for each of said
- M registers for each thread and whether ones of said N sets of values have been written to during execution of a dynamic execution thread.
A method comprising:
- updating a plurality of state bits for a register associated with each thread upon a write to said register by either of a parent thread or a dynamic execution thread;
- updating a thread specific register map value for each register write;
- reconciling said plurality of state bits upon termination of said dynamic execution thread to indicate the thread specific register map value for a correct thread.
An apparatus comprising:
- branch prediction logic to fork a dynamic execution thread from a parent thread in response to a branch instruction, wherein said branch prediction logic is also to determine a correct thread;
- a register map to store two pointers for a register and a plurality of state bits for said register, said register map to update said plurality of state bits in response to a write from either said dynamic execution thread or said parent thread during dynamic execution;
- recovery logic to update said plurality of state bits to indicate which of the two pointers indicates the correct thread.
A register renaming apparatus comprising:
- means for storing a register rename map;
- means for storing state for a first thread and a dynamically generated second thread;
- means for updating state when one of said first thread and said dynamically generated second thread is killed.
Dependencies are inferred from the claim text.