Processor and instruction control method

An instruction control method of executing instructions in accordance with dynamic pipeline scheduling, comprising:

• an instruction issuing step wherein the instructions are issued by in-order;
• an instruction executing step wherein the instructions are executed by out-of-order;
• a committing step wherein a commitment of the instructions is discriminated by the in-order and said instructions are completed;
• an instruction discriminating step wherein whether all of a plurality of instructions which have simultaneously been fetched and decoded are symmetry instructions which can be arithmetically operated by different arithmetic operating units or there is an asymmetry instruction which can be arithmetically operated only by a specific arithmetic operating unit among said plurality of instructions and the residual instructions are said symmetry instructions is discriminated;
• a symmetry instruction issuing step wherein in the case where it is determined that all of said plurality of instructions are the symmetry instructions, said symmetry instructions are issued to a plurality of reservation stations provided for every different arithmetic operating units until they become full;
• and
• an asymmetry instruction issuing step wherein in the case where it is determined that the asymmetry instruction exists among said plurality of instructions and the residual instructions are said symmetry instructions, said asymmetry instruction is developed into a multiflow of a previous flow and a following flow, said asymmetry instruction is issued to the reservation station provided in correspondence to said specific arithmetic operating unit, and the residual symmetry instructions are issued to said plurality of reservation stations provided for said every different arithmetic operating units in an issuing cycle different from that of said asymmetry instruction until they become full.