Loading patent…
AssigneeInternational Business Machines Corporation
InventorsJaime Humberto Moreno, Fredy Daniel Neeser
Estimating the term…
A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal processor (DSP) that is based on single-instruction-multiple-data (SIMD) principles and provides indirect access to vector elements. The disclosed configuration uses a processor with two vector units and associated registers, where the vector units are connected back to back for processing Viterbi decoder state metrics. Viterbi add instructions increment vectors of state metrics from a first register, performing a desired permutation of state metrics while reading them indirectly through vector pointers, and writing intermediate result vectors to a second register. Viterbi select instructions perform element-wise maximum or minimum operations on vectors from the second register to determine survivor metrics, performing a desired inverse permutation of survivor metrics while writing them back to the first register and recording the corresponding decisions in a shift register for use in a subsequent traceback operation.
A programmable digital signal processing device for implementing a Viterbi algorithm having a plurality of add-compare-select operations (ACS) operating on a plurality of Viterbi state metrics, the device comprising:
A method of performing a first compute-and-move instruction comprising performing a first vector operation on source operands from a first vector unit and placing the results of the first vector operation into a second vector unit.
A method for operating a first vector unit and a second vector unit in tandem, the method comprising performing a first compute-and-move instruction by performing a first vector operation on source operands from the first vector unit and placing the results of the first vector operation into the second vector unit and
A method for operating a first vector unit and a second vector unit in tandem, the method comprising performing a first compute-and-move instruction by performing a first vector operation on source operands from the first vector unit and placing the results of the first vector operation into the second vector unit and
A method for operating a first vector unit and a second vector unit in tandem, the method comprising performing a first compute-and-move instruction by performing a first vector operation on source operands from the first vector unit and placing the results of the first vector operation into the second vector unit and
A method for implementing in a programmable digital signal processing device a Viterbi algorithm comprising a plurality of add-compare-select operations (ACS) operating on a plurality of Viterbi state metrics, the method comprising the step of:
A method for implementing in a programmable digital signal processing device a Viterbi algorithm comprising a plurality of add-compare-select operations (ACS) operating on a plurality of Viterbi state metrics, the method comprising the step of:
A method for implementing in a programmable digital signal processing device a Viterbi algorithm comprising a plurality of add-compare-select operations (ACS) operating on a plurality of Viterbi state metrics, the method comprising the step of:
A computer program comprising program code means for performing a method of performing a first compute-and-move instruction when said program is run on a programmable digital signal processor, the method comprising performing a first vector operation on source operands from a first vector unit and placing the results of the first vector operation into a second vector unit.
A computer program comprising program code means for performing a method of operating a first vector unit and a second vector unit in tandem when said program is run on a programmable digital signal processor, the method comprising performing a first compute-and-move instruction by performing a first vector operation on source operands from the first vector unit and placing the results of the first vector operation into the second vector unit and
A computer program comprising program code means for performing a method of implementing a Viterbi algorithm comprising a plurality of add-compare-select operations (ACS) operating on a plurality of Viterbi state metrics when said program is run on a programmable digital signal processor, the method comprising performing in a first vector unit and a second vector unit concurrent operations for executing a subset of the plurality of add-compare-select operations (ACS).
A computer program product stored on a computer usable medium, comprising computer readable program means for causing a programmable digital signal processor to perform a method of performing a first compute-and-move instruction, the method comprising performing a first vector operation on source operands from a first vector unit and placing the results of the first vector operation into a second vector unit.
A computer program product stored on a computer usable medium, comprising computer readable program means for causing a programmable digital signal processor to perform a method of operating a first vector unit and a second vector unit in tandem, the method comprising performing a first compute-and-move instruction by performing a first vector operation on source operands from the first vector unit and placing the results of the first vector operation into the second vector unit and
A computer program product stored on a computer usable medium, comprising computer readable program means for causing a programmable digital signal processor to perform a method of implementing a Viterbi algorithm comprising a plurality of add-compare-select operations (ACS) operating on a plurality of Viterbi state metrics, the method comprising performing in a first vector unit and a second vector unit concurrent operations for executing a subset of the plurality of add-compare-select operations (ACS).
Dependencies are inferred from the claim text.