Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses
AssigneeMicron Technology, Inc.
InventorKevin Duncan
Life of this patent
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Abstract
A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.
Claims66
A method for testing a memory circuit, the method comprising:
- multiplying a first number in a sequence of deterministic pseudo-random numbers by a multiplier;
- discarding all of the product of said act of multiplying except for a first plurality of low order bits representing a portion of said product, said first plurality of low order bits also representing a first memory address;
- and
- testing a portion of said memory circuit represented by said first memory address.
A method for testing a memory circuit, the method comprising:
- generating a first number in a sequence of deterministic pseudo-random numbers, said first number representing a first portion of a first address within said memory circuit to be tested;
- combining said first address portion with a second address portion to form said first address;
- and
- testing a portion of said memory circuit represented by said first address.
A method for forming a sequence of memory addresses, the method comprising:
- multiplying an initial value by a multiplier;
- discarding all of the product of said first multiplying operation except for a first plurality of low order bits;
- forwarding said first plurality of low order bits to a memory address builder for forming a first memory address;
- multiplying said first plurality of low order bits by said multiplier;
- discarding all of the product of said second multiplying operation except for a second plurality of low order bits;
- and
- forwarding said second plurality of low order bits to said memory address builder for forming a second memory address.
A system for forming a sequence of memory addresses, the system comprising:
- a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers;
- and
- an address builder coupled to an output of said pseudo-random number generator for receiving said first plurality of bits and combining said first plurality of bits with a second plurality of bits, such that said combined first and second plurality of bits form a first memory address.
A system for forming a memory address, the system comprising:
- a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers, said first pseudo-random number representing at least a portion of a first memory address;
- and
- a pattern eliminator coupled to said pseudo-random number generator and configured to receive at least a portion of said first plurality of low order bits and to remove a pattern that exists in said portion.
A memory card containing a system for forming a memory address, the system comprising:
- a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers;
- and
- an address builder coupled to an output of said pseudo-random number generator for receiving said first plurality of bits and combining said first plurality of bits with a second plurality of bits, such that said combined first and second plurality of bits form a first memory address.
A memory card containing a system for forming a memory address, the system comprising:
- a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers, said first pseudo-random number representing at least a portion of a first memory address;
- and
- a pattern eliminator coupled to said pseudo-random number generator and configured to receive at least a portion of said first plurality of low order bits and to remove a pattern that exists in said portion.
A processor system, comprising:
- a central processing unit;
- a memory card coupled to said processor, said memory card containing a system for forming a memory address, the system comprising:
- a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers;
- and
- an address builder coupled to an output of said pseudo-random number generator for receiving said first plurality of bits and combining said first plurality of bits with a second plurality of bits, such that said combined first and second plurality of bits form a first memory address.
A processor system, comprising:
- a central processing unit;
- a memory card coupled to said processor, said memory card containing a system for forming a memory address, the system comprising:
- a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers, said first pseudo-random number representing at least a portion of a first memory address;
- and
- a pattern eliminator coupled to said pseudo-random number generator and configured to receive at least a portion of said first plurality of low order bits and to remove a pattern that exists in said portion.
Dependencies are inferred from the claim text.