Address translation apparatus, address translation method, and two-layer address translation apparatus
AssigneeFujitsu Limited
InventorsTakuma Chiba, Tsuyoshi Motokurumada, Iwao Yamazaki
Life of this patent
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Abstract
A first table stores operand data for translation of operand virtual address into a physical address. A second table stores instruction data for translation of instruction virtual address into a physical address. The first and the second tables are formed in one memory. If operand access and instruction access are generated simultaneously, the operand access is executed with priority and the instruction virtual address is held in a wait register after that the instruction access is executed after finishing the operand access based on a wait instruction virtual address.
Claims14
An address translation apparatus comprising:
- an address translation buffer including an operand address translation buffer, which stores operand address translation data for translation of an operand virtual address into a physical address, and an instruction address translation buffer, which stores instruction address translation data for translation of an instruction virtual address into a physical address, the operand address translation buffer and the instruction address translation buffer having a fixed area and sharing the same memory;
- an operand access control unit that carries out control to execute an operand access with priority, and to hold an instruction virtual address corresponding to an instruction access, when an access collision has occurred that the operand access to the operand address translation buffer and the instruction access to the instruction address translation buffer are generated at the same time;
- and
- an instruction access control unit that carries out control to execute an instruction access after finishing the operand access, and to translate the instruction virtual address held into a physical address based on data stored in the instruction address translation buffer.
An address translation method that uses an address translation buffer including an operand address translation buffer, which stores operand address translation data for translation of an operand virtual address into a physical address, and an instruction address translation buffer, which stores instruction address translation data for translation of an instruction virtual address into a physical address, the operand address translation buffer and the instruction address translation buffer having a fixed area and sharing the same memory, the address translation method comprising:
- an operand access control step of carrying out control to execute an operand access with priority, and to hold an instruction virtual address corresponding to an instruction access, when an access collision has occurred that the operand access to the operand address translation buffer and the instruction access to the instruction address translation buffer are generated at the same time;
- and
- an instruction access control step of carrying out control to execute an instruction access after finishing the operand access, and to translate the held instruction virtual address into a physical address by using the instruction address translation buffer.
A two-layer address translation apparatus comprising:
- a lower address translating unit having
- an address translation buffer including an operand address translation buffer, which stores operand address translation data for translation of an operand virtual address into a physical address, and an instruction address translation buffer, which stores instruction address translation data for translation of an instruction virtual address into a physical address, the operand address translation buffer and the instruction address translation buffer having a fixed area and sharing the same memory;
- an operand access control unit that carries out control to execute an operand access with priority, and hold an instruction virtual address corresponding to an instruction access, when an access collision has occurred that the operand access to the operand address translation buffer and the instruction access to the instruction address translation buffer are generated at the same time;
- and
- an instruction access control unit that carries out control to execute an instruction access after finishing the operand access, and translating the held instruction virtual address into a physical address by using the instruction address translation buffer;
- a higher operand address translating unit that can be accessed at a higher speed than the operand address translation buffer, and that holds a part of operand address translation data stored in the operand address translation buffer, translates the operand virtual address into the physical address according to the operand access, and requests the lower address translating unit to carry out the translation when it is not possible to carry out the translation;
- and
- a higher instruction address translating unit that can be accessed at a higher speed than the instruction address translation buffer, and that holds a part of instruction address translation data stored in the instruction address translation buffer, translates the instruction virtual address into the physical address according to the instruction access, and requests the lower address translating unit to carry out the translation when it is not possible to carry out the translation.
Dependencies are inferred from the claim text.