Method for bus capacitance reduction
AssigneeMicron Technology, Inc.
InventorDean A. Klein
Life of this patent
Estimating the term…
Abstract
Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.
Claims15
A method of accessing data storage locations in a memory circuit comprising the acts of:
- issuing at least one memory access control signal to a first portion of said memory circuit;
- and
- coupling a data bus to a second portion of said memory circuit in response to said at least one memory access control signal.
A method of accessing data storage locations in a memory circuit comprising the acts of:
- issuing at least one memory access control signal to a first portion of said memory circuit, the signal comprising a row address strobe signal and a column address strobe signal;
- and
- coupling a data bus to a second portion of said memory circuit in response to said at least one memory access control signal, the coupling comprising closing a transfer gate in each line of said data bus.
A system for accessing data storage locations in a memory circuit comprising the acts of:
- means for issuing at least one memory access control signal to a first portion of said memory circuit;
- and
- means for coupling a data bus to a second portion of said memory circuit in response to said at least one memory access control signal.
A system for accessing data storage locations in a memory circuit comprising the acts of:
- means for issuing at least one memory access control signal to a first portion of said memory circuit, the signal comprising a row address strobe signal and a column address strobe signal;
- and
- means for coupling a data bus to a second portion of said memory circuit in response to said at least one memory access control signal, the coupling comprising closing a transfer gate in each line of said data bus.
A device for accessing data storage locations in a memory circuit comprising the acts of:
- a component for issuing at least one memory access control signal to a first portion of said memory circuit;
- and
- a component for coupling a data bus to a second portion of said memory circuit in response to said at least one memory access control signal.
A device for accessing data storage locations in a memory circuit comprising, the device comprising:
- a component for issuing at least one memory access control signal to a first portion of said memory circuit, the signal comprising a row address strobe signal and a column address strobe signal;
- and
- a component for coupling a data bus to a second portion of said memory circuit in response to said at least one memory access control signal, the coupling comprising closing a transfer gate in each line of said data bus.
Dependencies are inferred from the claim text.