System and method for multi-modal memory controller system operation
AssigneeHewlett-Packard Development Company, L.P.
InventorsJeff G. Hargis, George Thomas Letey, Michael Kennard Tayler
Life of this patent
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Abstract
A memory controller system for processing memory access requests comprising a first memory controller operable to address a first plurality of memory modules a second memory controller operable to address a second plurality of memory modules, the first and second memory controllers configurable to process a memory transaction in an operational mode of the memory controller system selected from the group consisting of an independent cell mode, a multiplexer-mode (mux-mode), and a lockstep mode, and a bus interface block operable to convey the memory transaction to both of the first and second memory controllers is provided.
Claims28
A memory controller system for processing memory access requests, comprising:
- a first memory controller operable to address a first plurality of memory modules;
- a second memory controller operable to address a second plurality of memory modules, the first and second memory controllers configurable to process a memory transaction in an operational mode of the memory controller system selected from the group consisting of an independent cell mode, a multiplexer-mode (mux-mode), and a lockstep mode;
- and
- a bus interface block operable to convey the memory transaction to both of the first and second memory controllers.
A method of processing a memory access request in a memory controller system, comprising:
- receiving, by the memory control system, a memory transaction;
- conveying the memory transaction to each of a first memory controller and a second memory controller;
- issuing, by the first memory controller, a memory command to a plurality of memory modules coupled with the first memory controller;
- and
- issuing, by the second memory controller, a memory command to a plurality of memory modules coupled with the second memory controller, wherein the issuing of the memory commands by the first and second memory controllers are performed in synchronization.
A method of configuring a memory controller system, comprising:
- indicating selection of a lockstep mode of the controller system;
- and
- transferring, to a first and second memory controller, configuration data writes addressed to a configuration register set of the first memory controller.
Dependencies are inferred from the claim text.