Cache memory device and memory allocation method
AssigneeFujitsu Limited
InventorsKumiko Endo, Masaki Ukai
Life of this patent
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Abstract
A cache memory device comprises a secondary tag RAM that partially constitutes a secondary cache memory and employs a set associative scheme having a plurality of ways, and a secondary cache access controller that, when the number of ways in the secondary tag RAM is changed, allocates tags to respective entries so that the total number of entries constituting the secondary tag RAM and the total number of entries after the number of ways is changed are constant.
Claims6
A cache memory device comprising:
- a cache memory that employs a set associative scheme having a plurality of ways;
- and
- an allocation unit that, when a number of ways is changed, allocates tags to respective entries so that a total number of entries constituting the cache memory and a total number of entries obtained after the number of ways is changed are constant.
A memory allocation method applied to a cache memory device with a cache memory that employs a set associative scheme having a plurality of ways, the memory allocation method comprising a step of:
- allocating tags to respective entries so that a total number of entries constituting the cache memory and a total number of entries obtained after the number of ways is changed are constant, when the number of ways is changed.
Dependencies are inferred from the claim text.