Methods and structure for hiding DRAM bank precharge and activate latency by issuing apriori bank state transition information
OwnerRobert W. Mossinventor
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OwnerRobert W. Mossinventor
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In a system having multiple master devices coupled to a shared resource, methods and structure for generating apriori information by an arbiter of the shared resource to enable the shared resource to better utilize the bandwidth of the shared resource. A first preferred embodiment of the invention provides an arbiter coupling a shared memory controller to a plurality of master devices generating memory requests for the memory controller. The arbiter preferably detects memory requests from another master device to detect when a next request is directed to a different bank of memory. Apriori information indicative of such a change in banks is sent to the memory controller in advance of the memory request that will require the change of banks. This apriori information enables the memory controller to control the sequence of commands applied to the memory subsystem to optimize utilization of the memory subsystem and hence improve system performance.
A method operable in an arbiter coupling a plurality of master devices to a memory controller controlling multiple banks of memory, said method comprising:
A method operable in an arbiter coupling a plurality of master devices to a shared resource to optimize utilization of said shared resource, said method comprising the steps of:
A system including a shared resource and a plurality of master devices, said system comprising:
A system operable in an arbiter coupling a plurality of master devices to a memory controller controlling multiple banks of memory, said system comprising:
Dependencies are inferred from the claim text.