System and method for efficient chip select expansion

A CPU system for sharing a select line, comprising:

• a controller;
• and
• a device select circuit including:
• a multiplexed bus including a chip select phase, an address phase, and a data phase;
• first controllable storage means for transferring chip select information from the multiplexed bus during the chip select phase to chip enable inputs of a plurality of connected devices;
• second controllable storage means for transferring address information from the multiplexed bus during the address phase to address inputs of the plurality of connected devices;
• wherein one of said plurality of connected devices is selected based on said device select circuit receiving signals consisting of the chip select information from the multiplexed bus and a single enable signal.

A chip select circuit, comprising:

• means for controlling access to a multiplexed bus having a chip select phase, an address phase, and a data phase;
• means for providing an address during an address phase;
• means for selecting one of a plurality of devices during a chip select phase;
• wherein said means for selecting enables the selected device in response to data consisting of chip select information carried on the multiplexed bus and a single chip enable signal.