Method and device of minimizing the number of LDRQ signal pin of LPC host and LPC host employing the same

A LDRQ controller for minimizing the number of LDRQ signal pin of a low pin count bus host, with said low pin count bus host is coupled to at least one LDRQ control device, said low pin count bus host is connected with a plurality of low pin count bus devices, said LDRQ controller being incorporated within said LDRQ control device, said LDRQ controller comprising:

• a decoding circuit for decoding LDRQ signals into DRQ signals;
• a DRQ control circuit used to have a priority arbitration process with received DRQ signals and DRQ signal issued by oneself;
• and
• an encoding circuit for translating received DRQ signals into LDRQ signals and transferring said LDRQ signals to either a LDRQ control device of next stage or a LDRQ signal pin of said low pin count bus host.

A method of minimizing the number of LDRQ signal pin of a low pin count bus host, said low pin count bus host is connected in series with at least one LDRQ control device, and said LDRQ device is connected with a plurality of low pin count bus devices, said method comprises the steps of:

• obtaining DRQ signals by decoding LDRQ signals received by said LDRQ control device;
• having a priority arbitration process with said DRQ signals and a DRQ signal issued by said LDRQ control device;
• and
• encoding a DRQ signal having a highest priority being resulted from said priority arbitration process into a LDRQ signal, transferring said LDRQ signal to either a LDRQ control device of next stage connected in series therewith or a LDRQ signal pin of said low pin count bus host.