HDP SRO liner for beyond 0.18 um STI gap-fill

A method of forming shallow trench isolation regions in the manufacture of an integrated circuit device comprising:

• growing a pad oxide layer on the surface of a substrate;
• depositing an etch stop layer overlying said pad oxide layer;
• etching an isolation trench through said etch stop layer and said pad oxide layer into said substrate;
• depositing a silicon-rich oxide liner layer overlying said substrate and within said isolation trench using a high density plasma chemical vapor deposition process (HDP-CVD);
• and
• depositing an oxide layer overlying said silicon-rich oxide liner layer and filling said trench using said HDP-CVD process to complete fabrication of said shallow trench isolation region in said manufacture of said integrated circuit device.

A method of forming shallow trench isolation regions in the manufacture of an integrated circuit device comprising:

• growing a pad oxide layer on the surface of a substrate;
• depositing an etch stop layer overlying said pad oxide layer;
• etching an isolation trench through said etch stop layer and said pad oxide layer into said substrate;
• growing a thermal oxide liner layer within said isolation trench;
• depositing a silicon-rich oxide liner layer overlying said substrate and within said isolation trench overlying said thermal oxide layer using a high density plasma chemical vapor deposition process (HDP-CVD) and
• depositing an oxide layer overlying said silicon-rich oxide liner layer and filling said trench using said HDP-CVD process to complete fabrication of said shallow trench isolation region in said manufacture of said integrated circuit device.