Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect

A method of using ternary copper alloy to obtain a low resistance and large grain size interconnect or via, the method comprising:

• providing a first conductive layer over an integrated circuit substrate;
• providing a conformal layer section at a bottom and sides of a via aperture positioned over the first conductive layer to form a barrier separating the via aperture from the first conductive layer;
• filling the via aperture with a ternary copper alloy via material to form a ternary copper alloy via;
• and
• providing a second conductive layer over the ternary copper alloy via such that the ternary copper alloy via electrically connects the first conductive layer to the second conductive layer.

A method of forming a via in an integrated circuit, the method comprising:

• depositing a first conductive layer;
• depositing an etch stop layer over the first conductive layer;
• depositing an insulating layer over the etch stop layer;
• forming an aperture in the insulating layer and the etch stop layer;
• providing a barrier material at a bottom and sides of the aperture to form a barrier layer;
• filling the aperture with a ternary copper alloy via material to form a ternary copper alloy via;
• and
• providing a second conductive layer over the ternary copper alloy via such that the ternary copper alloy via electrically connects the first conductive layer and the second conductive layer.