Method of manufacturing a MOS transistor
OwnerLien-Che Hoinventor
Life of this patent
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Abstract
A method of manufacturing MOS transistors is disclosed. The method includes a step of depositing a shield layer on a silicon substrate prior to forming source/drain regions. The shield layer is formed to cover a gate electrode and a field oxide layer (or shallow trench isolation) on a silicon substrate with a uniform thickness. Then, the silicon substrate is heavily implanted. The implanting energy is controlled to prevent ions from penetrating the shield layer at the sidewall region of the gate electrode. After removing the shield layer, the silicon substrate is processed with lightly implantation. In this way, a MOS transistor with LDD is formed with less manufacturing steps.
Claims16
A method of manufacturing a MOS transistor, comprising the steps of:
- forming a gate oxide, a gate electrode and a field oxide layer on a substrate;
- depositing a shield layer on said substrate to cover said gate electrode, said field oxide and said substrate surface with an uniform thickness, wherein said shield layer forms sidewall regions beside the gate electrode that has a thickness larger than the uniform thickness;
- forming a resist pattern on said substrate;
- implanting ions into said substrate to form heavily doped regions, wherein the implanting energy is controlled so that the ions cannot penetrate through said shield layer at the sidewall regions;
- removing said shield layer not covered by said resist pattern;
- implanting ions into said substrate to form lightly doped regions on said substrate;
- and
- removing said resist pattern and said residual shield layer.
A method of manufacturing a MOS transistor, comprising the steps of:
- forming a gate oxide, a gate electrode and shallow trench isolation (STI) on a substrate;
- depositing a shield layer on said substrate to cover said gate electrode, said field oxide and said substrate surface with an uniform thickness, wherein said shield layer forms sidewall regions beside the gate electrode that has a thickness larger than the uniform thickness;
- forming a resist pattern on said substrate;
- implanting ions into said substrate to form heavily doped regions, wherein the implanting energy is controlled so that the ions cannot penetrate through said shield layer at the sidewall regions;
- removing said shield layer not covered by said resist pattern;
- implanting ions into said substrate to form lightly doped regions on said substrate;
- and
- removing said resist pattern and said residual shield layer.
Dependencies are inferred from the claim text.