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US 2004/0003362 A1Published application
Timing abstraction and partitioning strategy
AssigneeLSI Logic Corporation
InventorChristopher L. Hamlin
Life of this patent
Estimating the term…
Abstract
The present invention is directed to a timing abstraction and partitioning strategy for integrated circuit design. A method for designing an integrated circuit may include monitoring user interaction with logical blocks during a function design process of an integrated circuit. Indications of timing properties are derived during the functional design process.
Claims27
A method of designing an integrated circuit, comprising:
- monitoring user interaction with logical blocks during a functional design process of an integrated circuit;
- and
- deriving indications of timing properties during the functional design process based on the monitored user interaction.
A system for designing an integrated circuit, comprising:
- a memory suitable for storing a program of instructions;
- and
- a processor communicatively coupled to the memory, the processor suitable for performing the program of instructions, wherein the program of instructions configures the processor to
- monitor user interaction with logical blocks during a functional design process of an integrated circuit;
- and
- derive indications of timing properties during the functional design process based on the monitored user interaction.
3 more elements
A system for designing an integrated circuit, comprising:
- means for monitoring user interaction with logical blocks during a functional design process of an integrated circuit;
- and
- means for deriving indications of timing properties during the functional design process, the deriving means communicatively coupled to the monitoring means.
Dependencies are inferred from the claim text.