US 2004/0003361 A1 · Dynamically reconfiguring clock domains on a chip

Abstract

Disclosed is an integrated circuit that includes clock generation circuitry which generates a master clock signal and at least one other clock signal. The master clock signal and the other clock signal are transmitted through a clock distribution tree to a circuit component. In a default mode, the circuit component receives the master clock signal at a first component block to create a first time domain for the first component block and receives the other clock signal at a second component block to create a second time domain for the second component block. Bypass logic creates a bypass path to allow the second component block to receive the master clock signal such that the clock domain of the second component block is the same as the clock domain of the first component block such that signals can be transferred between the clock domains with reduced latency.

Claims28

Dependent claims

An integrated circuit comprising:

clock generation circuitry to generate a master clock signal and at least one other clock signal transmitted through a clock distribution tree to a circuit component, the circuit component receiving the master clock signal at a first component block;
and
bypass logic to define a bypass path to allow a second component block of the circuit component to receive the master clock signal, wherein the first and second components are controlled by a common clock domain in response to the master clock signal.

Dependencies are inferred from the claim text.

Dynamically reconfiguring clock domains on a chip

Life of this patent

Dynamically reconfiguring clock domains on a chip

Life of this patent

Abstract

Claims28