Systems and methods for time-budgeting a complex hierarchical integrated circuit

A method for determining signal propagation delay in an integrated circuit representation, the method comprising the steps of:

• acquiring circuit information, the circuit information comprising a plurality of functional blocks and a plurality of conductors coupling the functional blocks, wherein the functional blocks are modeled by the conductors that traverse a border of the functional block;
• inserting a timing point in the circuit information;
• determining a delay time in response to the timing point;
• and
• deriving a constraint in response to the delay time.

A computer-readable medium having a program for generating a time budget for an integrated circuit, the program comprising:

• logic configured to receive a representation of the integrated circuit at a functional block level;
• logic configured to identify each of a plurality of conductors that traverse a border of a functional block of interest;
• logic configured to model the plurality of conductors;
• and
• logic configured to insert a timing point at the border of the functional block of interest.

A computer aided circuit design tool, comprising:

• means for acquiring a representation of an integrated circuit;
• means for analyzing the representation at a functional block level;
• means for determining a portion of a clock cycle that elapses before a signal that originates in an originating block traverses the interface of a functional block of interest;
• and
• means for deriving a first constraint that accounts for the portion of the clock cycle that elapses before the signal traverses the interface of the functional block of interest.