Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layout
AssigneePDF Solutions, Inc.
InventorsMichal Palusinski, Mariusz Niewczas, Wojciech Maly, Andrezej Stojwas, Thomas Waas, Hans Eisenmann
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Abstract
A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.
Claims15
A method to define a circuit pattern comprising identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern, without specifying edges that connect the vertices to each other.
A computer readable medium having computer program code encoded thereon, wherein, when the computer program code is executed by a processor, the processor executes a method for defining a circuit pattern comprising identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern, without specifying edges that connect the vertices to each other.
A system for defining a circuit pattern comprising:
- means for identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern, without specifying edges that connect the vertices to each other;
- and
- a storage device in which data representing the vertices and edges are stored.
Dependencies are inferred from the claim text.