Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure

A method comprising:

• encoding a data block to be written to a memory comprising a plurality of memory devices with a plurality of check bits to generate an encoded data block, wherein the plurality of check bits are defined to provide at least:
• (i) detection and correction of a failure of one of the plurality of memory devices;
• and (ii) detection and correction of a single bit error in the encoded data block following detection of the failure of one of the plurality of memory devices;
• and
• writing the encoded data block to the memory.

An apparatus comprising:

• means for encoding a data block to be written to a memory comprising a plurality of memory devices with a plurality of check bits to generate an encoded data block, wherein the plurality of check bits are defined to provide at least:
• (i) detection and correction of a failure of one of the plurality of memory devices;
• and (ii) detection and correction of a single bit error in the encoded data block following detection of the failure of one of the plurality of memory devices;
• and
• means for writing the encoded data block to the memory.

A memory controller comprising:

• a check bit encoder circuit coupled to receive a data block to be written to a memory comprising a plurality of memory devices, wherein the check bit encoder circuit is configured to encode the data block with a plurality of check bits to generate an encoded data block, wherein the plurality of check bits are defined to provide at least:
• (i) detection and correction of a failure of one of the plurality of memory devices;
• and (ii) detection of a double bit error in the encoded data block following detection of the failure of one of the plurality of memory devices;
• wherein the memory controller is configured to write the encoded data block to the memory;
• and
• a check/correct circuit coupled to receive the encoded data block from the memory and configured to decode the encoded data block and perform at least the detection of (i) and (ii) on the encoded data block;
• wherein the encoded data block is logically arranged as an array of rows (0 to R−1) and columns (0 to C−1) of bits, wherein each column comprises the bits stored in a different one of the plurality of memory devices, and wherein the plurality of check bits include a plurality of auxiliary check bits and a plurality of inner check bits, wherein the plurality of auxiliary check bits are stored in a first column of the array, and wherein each of the plurality of auxiliary check bits is in a row of the array and covers bits in the other columns of the array, and wherein each of the plurality of inner check bits covers selected bits of the encoded data block except for the plurality of auxiliary check bits, and wherein each bit of the array except for the plurality of auxiliary check bits has an associated assignment of one or more of the plurality of inner check bits that covers that bit, wherein the assignments are selected to satisfy the following, where syn(rx, cy) is the inner syndrome associated with the bit at row x, column y of the array and XOR is bitwise exclusive OR:
• for any set of rows R1 of the array, wherein R1 is not an empty set, and for any set of columns c1 and c2 of the array, wherein cl is not equal to c2, an XOR of the syndromes over each position (r, c), where r is an element of R and c is an element of (c1, c2), is not equal to zero;
• and
• for any set of 2 distinct rows r1 and r2 and any set of 3 distinct columns c1, c2, and c3, syn(r1, c1) XOR syn (r2, c2) XOR syn(r1, c3) XOR syn(r2, c3) is not equal to zero.

A communication system comprising:

• a check bit encoder circuit coupled to receive a data block to be transmitted via a transmission medium comprising a plurality of paths, wherein the check bit encoder circuit is configured to encode the data block with a plurality of check bits to generate an encoded data block, wherein the plurality of check bits are defined to provide at least:
• (i) detection and correction of a failure of one of the plurality of paths;
• and (ii) detection and correction of a single bit error in the encoded data block following detection of the failure of one of the plurality of paths;
• and
• a check/correct circuit coupled to receive the encoded data block from the transmission medium and configured to decode the encoded data block and perform at least the detection of (i) and (ii) on the encoded data block.

A communication system comprising:

• a check bit encoder circuit coupled to receive a data block to be transmitted via a transmission medium comprising a plurality of paths, wherein the check bit encoder circuit is configured to encode the data block with a plurality of check bits to generate an encoded data block, wherein the plurality of check bits are defined to provide at least:
• (i) detection and correction of a failure of one of the plurality of paths;
• and (ii) detection of a double bit error in the encoded data block following detection of the failure of one of the plurality of paths;
• and
• a check/correct circuit coupled to receive the encoded data block from the transmission medium and configured to decode the encoded data block and perform at least the detection of (i) and (ii) on the encoded data block;
• wherein the encoded data block is logically arranged as an array of rows (0 to R−1) and columns (0 to C−1) of bits, wherein each column comprises the bits transmitted via a different one of the plurality of paths, and wherein the plurality of check bits include a plurality of auxiliary check bits and a plurality of inner check bits, wherein the plurality of auxiliary check bits are in a first column of the array, and wherein each of the plurality of auxiliary check bits is in a row of the array and covers bits in the other columns of the array, and wherein each of the plurality of inner check bits covers selected bits of the encoded data block except for the plurality of auxiliary check bits, and wherein each bit of the array except for the plurality of auxiliary check bits has an associated assignment of one or more of the plurality of inner check bits that covers that bit, wherein the assignments are selected to satisfy the following, where syn(rx, cy) is the inner syndrome associated with the bit at row x, column y of the array and XOR is bitwise exclusive OR:
• for any set of rows R1 of the array, wherein R1 is not an empty set, and for any set of columns c1 and c2 of the array, wherein c1 is not equal to c2, an XOR of the syndromes over each position (r, c), where r is an element of R and c is an element of (c1, c2), is not equal to zero;
• and
• for any set of 2 distinct rows r1 and r2 and any set of 3 distinct columns c1, c2, and c3, syn(r1, c1) XOR syn (r2, c2) XOR syn(r1, c3) XOR syn(r2, c3) is not equal to zero.