Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith

A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern, comprising:

• for each of one or more blocks of core test patterns for each core under test;
• processing each of said core test patterns including loading the test pattern into scannable memory element scan chains in said core at a respective core clock rate, capturing the response of the circuit to the core test pattern, unloading the test response from the memory elements, and compressing the test response into a core test response signature register;
• concurrently with said processing, loading a test block expected signature into a core expected signature register at a common test clock rate;
• upon completion of processing of each block of test patterns, replacing the test response signature in said test response signature register with said test block expected signature;
• and
• identifying a block of test patterns as a failing test block when said test response signature is different from said test block expected signature.

A test controller for use in self-testing of an integrated circuit under control of a first clock and providing real time identification of failing test patterns, the controller having a test response signature register for storing a compressed test response of the circuit to a test patterns, comprising:

• an expected signature register having a serial input, a serial output, and a bit length which is at least equal to the bit length of said test response signature register;
• a pattern counter for counting test patterns which have been executed;
• a control circuit for controlling loading of said expected signature register under control of a test clock and for replacing the contents of said test response signature register with the contents of said expected signature register, said control circuit having a bit counter for counting the number of bits loaded into said test expected signature register, said control circuit being responsive to a predetermined test pattern count of said pattern counter for replacing the contents of said test response signature with the contents of said expected signature register;
• an asynchronous interface circuit for synchronizing shift operations of said expected signature register when shift operations are performed under control of a second clock;
• and
• a serial input connected to said expected signature register serial input for loading an expected signature into said controller.