Method and apparatus for implementing fault detection and correction in a computer system that requires high reliability and system manageability

A method comprising:

• during normal operation of a processor, periodically re-starting a first stage of a multi-stage watch-dog timer;
• if the first stage of the watch-dog timer times out,
• starting a second stage of the multi-stage watch-dog timer;
• sending a first interrupt to the processor;
• and
• sending a first signal to a system management controller to log data related to a fault on the computer;
• and
• if the second stage of the watch-dog timer times out before the second stage is re-set by the processor,
• starting a third stage of the watch-dog timer;
• sending a second interrupt to the processor;
• and
• sending a second signal to the system management controller to log data related to the fault on a computer;
• and
• if the third stage of the watch-dog timer times out before it is re-set by the processor,
• re-starting the computer.

A machine-readable medium having stored thereon a plurality of executable instructions, the plurality of instructions comprising instructions to:

• re-start a first stage of a multi-stage watch-dog timer;
• if the first stage of the watch-dog timer times out before the first-stage is re-started by a processor,
• start a second stage of the multi-stage watch-dog timer;
• send a first interrupt to the processor;
• and
• send a first signal to a system management controller to log data related to a fault on the computer;
• and
• if the second stage of the watch-dog timer times out before the second stage is re-set by the processor,
• start a third stage of the watch-dog timer;
• send a second interrupt to the processor;
• and
• send a second signal to the system management controller to log data related to the fault on a computer;
• and
• re-start the computer, if the third stage of the watch-dog timer times out before it is re-set by the processor.

A multi-stage watch dog timer to monitor operations of a computer comprising:

• a first stage to count to a first pre-determined terminal count, wherein if the first stage times out, the multi-stage watch dog timer to send event information to a system management controller and to send a first interrupt to a processor;
• a second stage to count to a second pre-determined terminal count, wherein if the first stage times out, the second stage is started, and the multi-stage watch dog timer to send event information to the system management controller and send a second interrupt to the processor;
• and
• a third stage to count to a third pre-determined terminal count, wherein if the second stage times out, the third stage is started, and the multi-stage watch dog timer to set a faulty bit if the third stage times out.

A processor management method comprising:

• periodically re-starting a first stage of a multi-stage watch dog timer during normal operation;
• responsive to received first or second interrupts, beginning an interrupt service routine to diagnose a fault;
• restarting an application if the fault is not diagnosed;
• and
• responsive to a third interrupt, re-starting the processor.

A system comprising:

• a multi-stage watch dog timer to count to predetermined first, second and third terminal counts;
• a central processing unit to receive an interrupt if the first and second terminal counts are reached and responsive to the interrupt begin an interrupt service routine to diagnose a fault;
• and
• a system management controller to receive data related to the fault.