Techniques for utilization of asymmetric secondary processing resources
AssigneeIntel Corporation
InventorsZhong-Ning Cai, Chee How Lim
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Abstract
A processor having asymmetric secondary processing resources. One disclosed embodiment includes a first execution resource to perform a first function and a second execution resource that also performs the second function, although the second processing resource is asymmetric to the first resource in that it has a lower throughput than the first processing resource. Switching logic switches execution from the first processing resource to the second processing resource in a reduced power consumption mode.
Claims51
An apparatus comprising:
- a first processing resource to perform a first function;
- a second processing resource to also perform said first function, said second processing resource being asymmetric in throughput with respect to said first processing resource;
- switching logic to switch execution from said first processing resource in a first mode to said second processing resource in an reduced power consumption mode.
An apparatus comprising:
- a first processor pipeline segment;
- a second processor pipeline segment, said second processor pipeline segment being a simple processor pipeline segment relative to said first processor pipeline segment;
- pipeline switch logic to switch execution from said first processor pipeline segment in a first mode to said second processor pipeline segment in a low power consumption mode.
A method comprising:
- executing instructions via a first execution resource in a first mode;
- transitioning to a low power mode;
- executing instructions via a second execution resource in the low power mode.
A system comprising:
- a memory to store a plurality of instructions;
- a processor to execute said plurality of instructions using either a first set of resources or a second asymmetric set of resources, said processor to produce a same result using either said first set of resources or said second set of resources, said processor to use said first set of resources in a first mode and to use said second set of resources in a second mode.
A processor comprising:
- an in-order pipeline;
- an out-of-order-pipeline;
- a plurality of registers accessible by both the in-order pipeline and said out-of-order pipeline;
- a plurality of execution units operative in response to instructions processed by said in-order pipeline and said out-of-order pipeline.
An apparatus comprising:
- first means for performing a first processing function;
- second means for performing said first processing function;
- means for switching between use of said first processing function and said second processing function.
Dependencies are inferred from the claim text.