Fixed point unit power reduction mechanism for superscalar loop execution

A system for reducing power consumption in a computing device when the computing device executes instructions in a tight loop, the computing device including a data cache, a data latch that latches data from the data cache, a table look up buffer, and an effective address translation unit, the system comprising:

• an address generation unit that generates an address for an operand, the address being used by the table look up buffer and the effective address translation unit to retrieve the operand;
• a first carry-out detecting unit that detects a first carry-out condition in a first preselected bit in the address generation unit;
• a first logic circuit that causes new data to be retrieved from the data cache and latched into the data latch when the first carry-out detecting unit detects the first carry-out condition from the first preselected bit;
• and
• a second logic circuit that causes the operand to be obtained from the data latch without accessing the data cache, thereby reducing power consumed by the data cache when the first carry-out detecting unit does not detect the first carry-out condition from the first preselected bit.