Security processor with bus configuration
AssigneeNXP B.V.
InventorThorwald Rabeler
Life of this patent
Estimating the term…
Abstract
A security subsystem controls the data transfer rights among components of a secured system via a common bus. The security subsystem includes a secure block that is coupled to an access controller, preferably via a hard-wired connection to the controller. This secure block exclusively controls the access rights among components, and can effectively isolate security functions and data from the main processor. Because the security is provided via access control to components or subsets of components via a common bus, an efficient and effective integration of the security subsystem within the secured system can be achieved.
Claims14
A system comprising:
- a main processor that is configured to effect a primary function of the system,
- a plurality of components that are configured to transfer data via a bus that is common to the main processor,
- an access controller that is configured to selectively inhibit data transfers between the main processor and one or more components of the plurality of components, based on defined access rights, and
- a secure block that is independent of the main processor and is configured to define the access rights.
A method for securing a protected system having a common bus for data transfers among a plurality of components, a main processor, and a secure block, the method comprising:
- defining access rights among the plurality of components, the main processor, and the secure block, and
- inhibiting select data transfers on the common bus, based on the access rights among the plurality of components, the main processor, and the secure block,
- wherein
- the access rights are defined by the secure block, independent of the main processor.
Dependencies are inferred from the claim text.