Loop control circuit and loop control method

A loop control circuit comprising:

• a means for storage that pushes down a loop leading address, the value indicating the number of loop executions and a loop trailing address indicated in a loop instruction being initially executed into a loop leading address stack, a loop number stack and a loop trailing address stack respectively, and stores the address of the instruction immediately preceding said loop instruction, the loop leading address, the value indicating the number of loop executions and the loop trailing address into a loop instruction register;
• a means for loop instruction recurrence prediction that predicts a recurrence of said loop instruction by comparing the address of the instruction immediately preceding said loop instruction, which is stored in said loop instruction register, with a program counter value;
• and
• a means for push down that adds the number of words constituting said loop instruction to the program counter value, and also pushes down the loop leading address, the value indicating the number of loop executions and the loop trailing address stored in said loop instruction register into an said loop leading address stack, said loop number stack and said loop trailing address stack respectively when the address of the instruction immediately preceding said loop instruction stored in said loop instruction register matches the program counter value and accordingly, it is predicted that said loop instruction is to occur next.

A loop control circuit comprising:

• a means for storage that pushes down a loop leading address, the value indicating the number of loop executions and a loop trailing address indicated in a loop instruction being initially executed into a loop leading address stack, a loop number stack and a loop trailing address stack respectively, and stores the address of the instruction immediately preceding said loop instruction, the value indicating the number of loop executions and the loop trailing address into a loop instruction register;
• a means for loop instruction recurrence prediction that predicts a recurrence of said loop instruction by comparing the address of the instruction immediately preceding said loop instruction, which is stored in said loop instruction register, with a program counter value;
• and
• a means for push down that adds the number of words constituting said loop instruction to the program counter value, pushes down the new program counter value obtained by the number of words as the loop leading address into said loop leading address stack, and also pushes down the value indicating the number of loop executions and the loop trailing address stored in said loop instruction register into said loop number stack and said loop trailing address stack respectively, when the address of the instruction immediately preceding said loop instruction stored in said loop instruction register matches the program counter value and, accordingly it is predicted that said loop instruction is to occur next.

A loop control circuit comprising:

• a means for storage that pushes down a loop leading address, the value indicating the number of loop executions and a loop trailing address of a loop instruction being initially executed into a loop leading address stack, a loop number stack and a loop trailing address stack respectively, and stores the address of the instruction immediately preceding said loop instruction, the loop leading address, the value indicating the number of loop executions and the loop trailing address into a single loop instruction register into which data were input first among a plurality of loop instruction registers;
• a means for loop instruction recurrence prediction that predicts a recurrence of said loop instruction by comparing the addresses of the instructions each immediately preceding a loop instruction in said plurality of loop instruction registers and a valid loop trailing address with a program counter value;
• and
• a means for push down that adds the number of words constituting said loop instruction to the program counter value and also pushes down the loop leading address, the value indicating the number of loop executions and the loop trailing address stored in a loop instruction register having the address of the instruction immediately preceding said loop instruction which matches the program counter value into said loop leading address stack, said loop number stack and said loop trailing address stack respectively, when the address of the instruction immediately preceding the loop instruction stored in one of said plurality of loop instruction registers matches the program counter value and the valid loop trailing address does not match the program counter value and, accordingly, it is predicted that said loop instruction is to occur next.

A loop control circuit comprising:

• a means for storage that pushes down a loop leading address, the value indicating the number of loop executions and the loop trailing address of a loop instruction being initially executed into a loop leading address stack, a loop number stack and a loop trailing address stack respectively, and stores the address of the instruction immediately preceding said loop instruction, the value indicating the number of loop executions and the loop trailing address into a single loop instruction register where the data were input first among a plurality of loop instruction registers;
• a means for loop instruction recurrence prediction that predicts a recurrence of said loop instruction by comparing the addresses of the instructions each immediately preceding a loop instruction stored in said plurality of loop instruction registers and a valid loop trailing address with a program counter value;
• and
• a means for push down that adds the number of words constituting said loop instruction to the program counter value, pushes down the new program counter value obtained by adding the number of words as the loop leading address into said loop leading address stack and also pushes down the value indicating the number of loop executions and the loop trailing address stored in a loop instruction register having the address of the instruction immediately preceding a loop instruction which matches the program counter value into said loop number stack and said loop trailing address stack respectively when the address of the instruction immediately preceding the loop instruction stored in one of said plurality of loop instruction registers matches the program counter value and the valid loop trailing address does not match the program counter value and, accordingly, it is predicted that said loop instruction is to occur next.

A loop control method comprising:

• a phase during which the address of a loop instruction at a second or subsequent stage in multiplexed loops is stored in memory when said loop instruction is initially executed;
• a phase during which a recurrence of said loop instruction at the second or subsequent stage is predicted by comparing the address of said loop instruction stored in memory with a value at a program counter;
• and
• a phase during which said loop instruction is skipped if it is predicted that said loop instruction is to occur next.

A loop control method comprising:

• a phase during which a loop leading address, the value indicating the number of loop executions and a loop trailing address indicated in a loop instruction being initially executed are pushed down into a loop leading address stack, a loop number stack and a loop trailing address stack respectively, and the address of the instruction immediately preceding said loop instruction, the loop leading address, the value indicating the number of loop executions and the loop trailing address are stored into a loop instruction register;
• a phase during which a recurrence of said loop instruction is predicted by comparing the address of the instruction immediately preceding said loop instruction, which is stored in said loop instruction register, with a program counter value;
• and
• a phase during which the number of words constituting said loop instruction is added to the program counter value, and the loop leading address, the value indicating the number of loop executions and the loop trailing address stored in said loop instruction register are pushed down into said loop leading address stack, said loop number stack and said loop trailing address stack respectively, when the address of the instruction immediately preceding said loop instruction stored in said loop instruction register matches the program counter value and accordingly, it is predicted that said loop instruction is to occur next.

A loop control method comprising:

• a phase during which a loop leading address, the value indicating the number of loop executions and a loop trailing address indicated in a loop instruction being initially executed are pushed down into a loop leading address stack, a loop number stack and a loop trailing address stack respectively, and the address of the instruction immediately preceding said loop instruction, the value indicating the number of loop executions and the loop trailing address into a loop instruction register;
• a phase during which a recurrence of said loop instruction is predicted by comparing the address of the instruction immediately preceding said loop instruction, which is stored in said loop instruction register, with a program counter value;
• and
• a phase during which the number of words constituting said loop instruction is added to the program counter value, the new program counter value obtained by the number of words is pushed down as the loop leading address into said loop leading address stack, and the value indicating the number of loop executions and the loop trailing address stored in said loop instruction register are pushed down into said loop number stack and said loop trailing address stack respectively, when the address of the instruction immediately preceding said loop instruction stored in said loop instruction register matches the program counter value and, accordingly it is predicted that said loop instruction is to occur next.

A loop control method comprising:

• a phase during which a loop leading address, the value indicating the number of loop executions and a loop trailing address indicated in a loop instruction being initially executed are pushed down into a loop leading address stack, a loop number stack and a loop trailing address stack respectively, and the address of the instruction immediately preceding said loop instruction, the loop leading address, the value indicating the number of loop executions and the loop trailing address are stored into a single loop instruction register where the data were input first among a plurality of loop instruction registers;
• a phase during which a recurrence of said loop instruction is predicted by comparing the addresses of the instructions each immediately preceding a loop instruction stored in said plurality of loop instruction registers and a valid loop trailing address with a program counter value;
• and
• a phase during which the number of words constituting said loop instruction is added to the program counter value and the loop leading address, the value indicating the number of loop executions and the loop trailing address stored in a loop instruction register having the address of the instruction immediately preceding said loop instruction which matches the program counter value are pushed down into said loop leading address stack, said loop number stack and said loop trailing address stack respectively when the address of the instruction immediately preceding the loop instruction stored in one of said plurality of loop instruction registers matches the program counter value and the valid loop trailing address does not match the program counter value and, accordingly, it is predicted that said loop instruction is to occur next.

A loop control method comprising:

• a phase during which a loop leading address, the value indicating the number of loop executions and a loop trailing address indicated in a loop instruction being initially executed are pushed down into a loop leading address stack, a loop number stack and a loop trailing address stack respectively, and the address of the instruction immediately preceding said loop instruction, the value indicating the number of loop executions and the loop trailing address are stored into a single loop instruction register where the data were input first among a plurality of loop instruction registers;
• a phase during which a recurrence of said loop instruction is predicted by comparing the addresses of the instructions each immediately preceding a loop instruction stored in said plurality of loop instruction registers and a valid loop trailing address with a program counter value;
• and
• a phase during which the number of words constituting said loop instruction is added to the program counter value, the new program counter value obtained by adding the number of words is pushed down as the loop leading address into said loop leading address stack and the value indicating the number of loop executions and the loop trailing address stored in a loop instruction register having the address of the instruction immediately preceding a loop instruction which matches the program counter value are pushed down into said loop number stack and said loop trailing address stack respectively, when the address of the instruction immediately preceding the loop instruction stored in one of said plurality of loop instruction registers matches the program counter value and the valid loop trailing address does not match the program counter value and, accordingly, it is predicted that said loop instruction is to occur next.