Instruction control method and processor

An instruction control method which uses delay instructions for branching, comprising:

• making a branch prediction;
• issuing an instruction by reading a corresponding delay instruction from the storage unit together with an instruction fetch request at a branching destination in a case where branching of an immediately preceding branch instruction becomes definite after issuing an instruction by temporarily replacing a delay instruction by a non-operation instruction when a corresponding branch instruction is predicted not to branch;
• and
• continuing execution of the instruction if an instruction at the predicted branching destination is issued and the predicted branching destination is correct and making an instruction refetch request of a branching destination instruction after the delay instruction if predicted branching destination is incorrect, after the branch instruction is predicted to branch and the corresponding delay instruction is issued.

An instruction control method which uses delay instructions for branching, comprising:

• making a branch prediction;
• and
• continuing execution of an instruction if no branching of an immediately preceding branch instruction becomes definite after no branching of a branch instruction is predicted and the instruction is issued by temporarily replacing a delay instruction by a non-operation instruction;
• and
• issuing the instruction immediately after a fetch is completed by making an instruction refetch request of an original sequential instruction if no branching of the branch instruction becomes definite after branching of the branch instruction is predicted.

A processor which carries out an instruction control using delay instructions for branching, comprising:

• a storage unit;
• a branch predictor making branch predictions;
• and
• a control unit successively storing a plurality of delay instructions in the storage unit together with information indicating whether or not branch instructions corresponding to the delay instructions are predicted to branch by the branch predictor.

A processor which carries out an instruction control using delay instructions for branching, comprising:

• a storage unit;
• a branch predictor making branch predictions.;
• and
• a control unit issuing an instruction by reading a corresponding delay instruction from the storage unit together with an instruction fetch request at a branching destination in a case where branching of an immediately preceding branch instruction becomes definite after issuing an instruction by temporarily replacing a delay instruction by a non-operation instruction when a corresponding branch instruction is predicted not to branch, and continuing execution of the instruction if an instruction at the predicted branching destination is issued and the predicted branching destination is correct and making an instruction refetch request of a branching destination instruction after the delay instruction if predicted branching destination is incorrect, after the branch instruction is predicted to branch and the corresponding delay instruction is issued.