Method for reducing the latency of a branch target calculation by linking the branch target address cache with the call-return stack

4) A circuit for reducing latency during a branch that references a CRS comprising:

• a BTAC, said BTAC having space for a first set of entries;
• a CRS, said CRS having space for a second set of entries;
• a group of electrical flags;
• wherein an electrical flag from said group of flags is included in each entry of said first set of entries;
• such that said electrical flag determines whether a target address in said BTAC should be used as the target of a branch operation or whether a address at the top of said CRS should be used as the target of said branch operation.

7) A circuit for reducing latency during a branch that references a CRS comprising:

• a BTAC, said BTAC having space for a first set of entries;
• a CRS, said CRS having space for a second set of entries;
• a means for tagging all entries in said first set of entries to indicate whether any entry in first set of entries references said CRS;
• a means for identifying any entry in said first set of entries that references said CRS;
• such that when an entry in said first set of entries is identified as containing a reference to said CRS, an address at the top of the CRS is used.