Program counter control method and processor
AssigneeFujitsu Limited
InventorsRyuichi Sunayama, Kuniki Morita, Aiichiro Inoue
Life of this patent
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Abstract
A program counter control method controls instructions by an out-of-order method using a branch prediction mechanism and controls an architecture having delay instructions for branching. The method includes the steps of simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction is successful and the branch instruction branches, and simultaneously updating a program counter and a next program counter depending on a number of committed instructions.
Claims18
A program counter control method for controlling instructions by an out-of-order method using a branch prediction mechanism and controlling an architecture having delay instructions for branching, comprising:
- simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction is successful and the branch instruction branches;
- and
- simultaneously updating a program counter and a next program counter depending on a number of committed instructions.
A program counter control method for controlling instructions by an out-of-order method using a branch prediction mechanism and controlling an architecture having delay instructions for branching, comprising:
- simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction is successful and the branch instruction does not branch;
- and
- simultaneously updating a program counter and a next program counter depending on a number of committed instructions.
A program counter control method for controlling instructions by an out-of-order method using a branch prediction mechanism and controlling an architecture having delay instructions for branching, comprising:
- simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction fails and the branch instruction branches;
- and
- simultaneously updating a program counter and a next program counter depending on a number of committed instructions.
A program counter control method for controlling instructions by an out-of-order method using a branch prediction mechanism and controlling an architecture having delay instructions for branching, comprising:
- simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction fails and the branch instruction does not branch;
- and
- simultaneously updating a program counter and a next program counter depending on a number of committed instructions.
A processor which controls instructions by an out-of-order method using a branch predictor and controls an architecture having delay instructions for branching, comprising:
- a branch instruction controller simultaneously controlling a plurality of branch instructions by judging branch conditions of the branch instructions, determining whether or not a branch prediction is successful and controlling an instruction refetch;
- and
- a branching destination address register storing a plurality of branching destination addresses of branch instructions branching of which is definite,
- said branching destination address register being controlled independently of said branch instruction controller and said branch predictor.
A processor which controls instructions by an out-of-order method using a branch predictor and controls an architecture having delay instructions for branching, comprising:
- a program counter section having a program counter and a next program counter;
- means for simultaneously committing a plurality of instructions including a branch instruction when a branch prediction is successful and the branch instruction branches;
- and
- means for simultaneously updating the program counter and the next program counter depending on a number of simultaneously committed instructions.
A processor which controls instructions by an out-of-order method using a branch predictor and controls an architecture having delay instructions for branching, comprising:
- a program counter section having a program counter and a next program counter;
- means for simultaneously committing a plurality of instructions including a branch instruction when a branch prediction is successful and the branch instruction does not branch;
- and
- means for simultaneously updating the program counter and the next program counter depending on a number of simultaneously committed instructions.
A processor which controls instructions by an out-of-order method using a branch predictor and controls an architecture having delay instructions for branching, comprising:
- a program counter section having a program counter and a next program counter;
- means for simultaneously committing a plurality of instructions including a branch instruction when a branch prediction fails and the branch instruction branches;
- and
- means for simultaneously updating the program counter and the next program counter depending on a number of simultaneously committed instructions.
A processor which controls instructions by an out-of-order method using a branch predictor and controls an architecture having delay instructions for branching, comprising:
- a program counter section having a program counter and a next program counter;
- means for simultaneously committing a plurality of instructions including a branch instruction when a branch prediction fails and the branch instruction does not branch;
- and
- means for simultaneously updating the program counter and the next program counter depending on a number of simultaneously committed instructions.
Dependencies are inferred from the claim text.