Instruction fetch control apparatus
AssigneeFujitsu Limited
InventorMasaki Ukai
Life of this patent
Estimating the term…
Abstract
When an instruction stored in a specific instruction buffer is the same as another instruction stored in another instruction buffer and logically subsequent to the instruction in the specific instruction buffer, a connection is made from the instruction buffer storing a logically and immediately preceding instruction, not the instruction in the other instruction buffer, to the specific instruction buffer without the instruction in the other instruction buffer, and a loop is generated by instruction buffers, thereby performing a short loop in an instruction buffer system capable of arbitrarily connecting a plurality of instruction buffers.
Claims16
An apparatus for controlling instruction fetch, comprising:
- an instruction buffer unit having a plurality of instruction buffers, and a pointer unit corresponding to the instruction buffers and indicating a connection relation of the instruction buffers;
- and
- a connection relation establishment unit establishing the connection relation between instruction buffers different from an instruction fetch request.
An method for controlling instruction fetch, comprising:
- having a plurality of instruction buffers, and a pointer unit corresponding to the instruction buffers and indicating a connection relation of the instruction buffers;
- and
- establishing the connection relation between instruction buffers different from an instruction fetch request.
Dependencies are inferred from the claim text.