Division on an array processor

Abstract

A component architecture for digital signal processing is presented. A two dimensional reconfigureable array of identical processors, where each processor communicates with its nearest neighbors, provides a simple and power-efficient platform to which convolutions, finite impulse response (“FIR”) filters, and adaptive finite impulse response filters can be mapped. An adaptive FIR can be realized by downloading a simple program to each cell. Each program specifies periodic arithmetic processing for local tap updates, coefficient updates, and communication with nearest neighbors. During steady state processing, no high bandwidth communication with memory is required. This component architecture may be interconnected with an external controller, or general purpose digital signal processor, either to provide static configuration or else supplement the steady state processing.

Dependencies are inferred from the claim text.