Address conversion apparatus, address conversion method and computer program
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsYoshihiro Tamura, Yutaka Tanase, Kiyohide Hori
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Abstract
An address output apparatus capable of retaining a pre-extension upper compatibility of software post memory extension and of accessing separated RAM areas by consecutive addresses, without needing to alter CPU architecture. The address output apparatus includes an address conversion circuit 20 that allots to a RAM 30 a basic RAM area and a first area, being one of two area obtained by dividing an extension RAM area, allots to a RAM 50 a second area, being an area other than the first area of the extension RAM area, and converts logical address signals designated by a CPU 10 to physical address signals based on a state of the allotting.
Claims9
An address conversion apparatus that outputs address signals for accessing readable/writable first and second memories, comprising:
- an acquisition unit operable to acquire a logical address value;
- and
- an output unit operable to output an address signal for accessing the first memory when the acquired logical address value is included in a first range, to output an address signal for accessing the first memory when the logical address value is included in a third range, which is a section within a second range, the second range being separated from the first range by an interval, and to output an address signal for accessing the second memory when the logical address value is included within the second range and not in the third range.
An address conversion method that outputs address signals for accessing readable/writable first and second memories, comprising:
- an acquisition step of acquiring a logical address value;
- and
- an output step of outputting an address signal for accessing the first memory when the acquired logical address value is included in a first range, outputting an address signal for accessing the first memory when the logical address value is included in a third range, which is a section within a second range, the second range being separated from the first range by an interval, and outputting an address signal for accessing the second memory when the logical address value is included within the second range and not in the third range.
A computer program executed by an address conversion apparatus that outputs address signals for accessing readable/writable first and second memories, comprising:
- an acquisition step of acquiring a logical address value;
- and
- an output step of outputting an address signal for accessing the first memory when the acquired logical address value is included in a first range, outputting an address signal for accessing the first memory when the logical address value is included in a third range, which is a section within a second range, the second range being separated from the first range by an interval, and outputting an address signal for accessing the second memory when the logical address value is included within the second range and not in the third range.
Dependencies are inferred from the claim text.