Burst transfer memory

A burst transfer memory comprising:

• a first memory having a cell array arranged in a matrix;
• a second memory which has a cell array arranged in a matrix and which performs a random access operation at a higher speed than the first memory;
• write and read data lines each connected to a corresponding column of the first and second memories;
• and
• an interface circuit which controls the first and second memories as one burst transfer memory, and
• wherein the second cell array is arranged adjacent to the first cell array in a bit line direction of the first cell array, and wherein the interface circuit allocates addresses to the first and second memories as consecutive addresses, and the interface circuit substantially simultaneously starts the first random access to the first and second memories, accesses the second memory before a word line of the first memory is activated, and consecutively accesses a page of the first memory after the word line of the first memory has been activated.

A burst transfer memory comprising:

• a first memory having a cell array arranged in a matrix;
• a second memory which has a cell array arranged in a matrix and which performs a random access operation at a higher speed than the first memory;
• first write and read data lines each connected to a corresponding column of the first memory;
• second write and read data lines each connected to a corresponding column of the second memory;
• an I/O circuit for the first memory which is connected to the first write and read data lines;
• an I/O circuit for the second memory which is connected to the second write and read data lines;
• and
• an interface circuit which controls the first and second memories as one burst transfer memory, and
• wherein the second memory is arranged adjacent to the first memory in a word line direction of the first memory, and
• wherein the interface circuit allocates addresses to the first and second memories as consecutive addresses, and the interface circuit substantially simultaneously starts the first random access to the first and second memories, accesses the second memory before a word line of the first memory is activated, and consecutively accesses a page of the first memory after the word line of the first memory has been activated.